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[Other] 二进制串行-1计数器

Description: 大学计算机数字逻辑实验作业 用Multisim仿真软件编写 计数器 用双D触发器74Ls74构成四位二进制串行计数器 二分频计数原理-University computer digital logic operations using Multisim experimental simulation software used to prepare counter-D Trigger 74Ls74 constitute four serial binary frequency counter two hours counting Principle
Platform: | Size: 27866 | Author: 赵传仕 | Hits:

[Other resource] maxshiyan

Description: 大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等，此原码基于长江大学可编程器件实验箱,如要运行在其他平台上需要重新定义管脚-University VHDL language experiment Daquan, based on the max-plus2 platform within 8-3 decoder, 8 Adder, digital clock, digital display, 74ls138, 8,4-bit counter, d, rs triggers, Adder, traffic lights, the original code based on the Yangtze University programmable devices experimental box, To run on other platforms need to be redefined pin
Platform: | Size: 865899 | Author: 田晶昌 | Hits:

[Other resource] MCU_Hardware_design_fundamental

Description: 单片机硬件系统设计原则一个单片机应用系统的硬件电路设计包含两部分内容：一是系统扩展，即单片机内部的功能单元，如ROM、RAM、I/O、定时器/计数器、中断系统等不能满足应用系统的要求时，必须在片外进行扩展，选择适当的芯片，设计相应的电路。二是系统的配置，即按照系统功能要求配置外围设备，如键盘、显示器、打印机、A/D、D/A转换器等，要设计合适的接口电路。 -MCU hardware design principles of a system based application system hardware circuit design includes two parts : First, the expansion of internal microcontroller that is the function modules, such as ROM, RAM, I / O, timer / counter, interrupt system can not meet the application requirements, must chip in for expansion, the selection of appropriate chips, The circuit design accordingly. Second, the system configuration, according to the functional requirements of system configuration peripheral equipment, such as keyboards, monitors, printers, A / D, D / A converters, it is necessary to design appropriate interface circuit.
Platform: | Size: 8115 | Author: wangtian | Hits:

[Other resource] ZZCPLD

Description: 本文详细介绍了制作电路板的方法及步骤. 实验板的功能 这个实验板可以做如下实验： 1．可以进行运算器（加、减、乘和除法）、比较器、译码器、编码器、选择器、分配器和一般组合电路的实验 2．可以进行触发器、寄存器、计数器和一般时序电路的实验 3．可以进行频率计电路、时钟电路、计时电路、交通灯等复杂数字系统的实验 4．加扩展板可以进行A/D、D/A、串行E2ROM和8031单片机等方面的实验 -This paper describes a circuit board production methods and steps. Experimental plate plate function of this experiment can be done is as follows Post-mortem : 1. Operators can (plus, subtraction, multiplication and division), comparators, decoder, the encoder, selectors, Distributor and the general composition of two circuits. Trigger can, register, counter and general sequential circuit of three. Can Cymometer circuit, clock circuit, the timer circuit, traffic lights and other complex digital system of four. Plus expansion boards can A / D, D / A, and 8031 Series MCU E2ROM areas of
Platform: | Size: 425460 | Author: cheng | Hits:

[Embeded-SCM Develop] DE2_Default

Description: his design is the initial design when the board is powered-up. It increments a counter and displays the value on the 7-segment displays and LEDs. An image is also displayed on the VGA port.-his design is the initial design when the bo ard is powered-up. It increments a counter and d isplays the value on the 7-segment displays and LEDs. An image is also displayed on the VGA port.
Platform: | Size: 270233 | Author: 木 易 | Hits:

[Other resource] 数据结构c描述习题集答案

Description: 减1计数器 一、设计要求 用Verilog HDL语言设计一个计数器。 要求计数器具有异步置位/复位功能，可以进行自增和自减计数，其计数周期为2^N（N为二进制位数）。 二、设计原理 输入/输出说明： d：异步置数数据输入； q：当前计数器数据输出； clock：时钟脉冲； count_en：计数器计数使能控制（1：计数/0：停止计数）； updown：计数器进行自加/自减运算控制（1：自加/0：自减）； load_d-a counter a reduction, design requirements using Verilog HDL design of a counter. Asynchronous requests with counter-home / reset functions can be carried out by self and self-count reduction, cycle counting of 2 ^ N (N for binary digit). Second, the principle of design input / output Description : d : asynchronous home several data input; Q : The current counter data output; Clock : clock pulse; Count_en : Counting enable control (1 : Counting / 0 : Stop counting); Updown : dollars several self-Canada / reduction Operational control (1 : Since the plus / 0 : Since decrease); load_d
Platform: | Size: 112206 | Author: tutu | Hits:

[Other] _Counter_

Description: 一个计数器dll，能统计进程的个数，只要进程装载它计数器会自动加一，进程卸载它就会自动减一，函数GetCount返回计数器的值-a counter dll, statistical process can number, as long as the process of loading it would counter an automatic, the process will automatically uninstall it by one, function GetCount counter to the values
Platform: | Size: 12288 | Author: 空了 | Hits:

[Other] 二进制串行-1计数器

Description: 大学计算机数字逻辑实验作业 用Multisim仿真软件编写 计数器 用双D触发器74Ls74构成四位二进制串行计数器 二分频计数原理-University computer digital logic operations using Multisim experimental simulation software used to prepare counter-D Trigger 74Ls74 constitute four serial binary frequency counter two hours counting Principle
Platform: | Size: 27648 | Author: 赵传仕 | Hits:

[SCM] 微机接口应用设计指导

Description: 微机原理与接口实验指导，包括：A/D转换实验、 D/A转换实验、255A并行口实验、定时器/计数器、数据排序程序、红绿交通灯实验等等 -computer interface experiment with the principles of the guide, include : A/D conversion experiments, the D/A conversion experiments, experimental 255A parallel port, timer/counter, data sequencing procedures, experimental black traffic lights, etc.
Platform: | Size: 529408 | Author: 张杰 | Hits:

[VHDL-FPGA-Verilog] maxshiyan

Description: 大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等，此原码基于长江大学可编程器件实验箱,如要运行在其他平台上需要重新定义管脚-University VHDL language experiment Daquan, based on the max-plus2 platform within 8-3 decoder, 8 Adder, digital clock, digital display, 74ls138, 8,4-bit counter, d, rs triggers, Adder, traffic lights, the original code based on the Yangtze University programmable devices experimental box, To run on other platforms need to be redefined pin
Platform: | Size: 865280 | Author: 田晶昌 | Hits:

[CSharp] d

Description: 哥赫巴德猜想 汉若塔 简单编码 简单计数器-Han哥赫巴德guess if the tower a simple coding simple counter
Platform: | Size: 1024 | Author: pingping | Hits:

[VHDL-FPGA-Verilog] bhgfdti

Description: 含有七人表决器，格雷码变换电路，英文字符显示电路，基本触发器（D和JK），74LS160计数器功能模块，步长可变的加减计数器-Containing seven people vote, and Gray code conversion circuit, the English characters display circuit, the basic flip-flop (D and JK), 74LS160 counter function modules, variable-step addition and subtraction counter
Platform: | Size: 423936 | Author: 俞皓尹 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 包括一个8位D触发器、一个jk触发器、一个10的计数器。适合初学者和开发人员-Including an 8-bit D flip-flop, a jk flip-flop, a 10-counter. Suitable for beginners and developers
Platform: | Size: 1024 | Author: 龚成 | Hits:

[Graph program] Counter

Description: KNN classifiers, training is training set, testing is test set, D is the distance, D=1 is mandistance D=2 is 欧氏距离 D=3是 infinite norm K is the number of selected neighbors- KNN classifiers, training is training set, testing is test set, D is the distance, D=1 is mandistance D=2 is 欧氏距离 D=3是 infinite norm K is the number of selected neighbors
Platform: | Size: 17408 | Author: 二 | Hits:

[VHDL-FPGA-Verilog] S_81

Description: 内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等-There are 8-3 decoder, 8-bit adder, digital clock, digital display, 74ls138, 8,4 bit counter, d, rs flip-flops, adders, traffic lights, etc.
Platform: | Size: 905216 | Author: fsdf | Hits:

[Other] counter

Description: MFC 实现计算器功能 实现计算器功能-MFC Calculator fg fgd dgd gfhd dfgd hdf hdf hdhdf hdfh d hdh hdfh dh dgh d hd hdh dh fsd
Platform: | Size: 49152 | Author: lrj | Hits:

[VHDL-FPGA-Verilog] BCD-counter

Description: 一个2位的BCD码十进制加法计数器电路，输入为时钟信号CLK，进位 输入信号CIN，每个BCD码十进制加法计数器的输出信号为D、C、B、A和进位输出信号COUT，输入时钟信号CLK用固定时钟，进位输入信号CIN. -A 2-bit BCD code decimal adder counter circuit input as the clock signal CLK, a carry input signal CIN, D, C, B, A, and the carry output signal COUT, each BCD code decimal adder counter' s output signal, the input clock signal CLK Fixed clock, binary input signal CIN.
Platform: | Size: 1024 | Author: victor | Hits:

[Software Engineering] counter

Description: 一、基础部分（70 ） 设计一个简易计算器，它具有下列运算功能： 1. 两个无符号的8位二进制数的相加； 2. 两个无符号的8位二进制数的相减； 3. 数值和运算符用4×4键盘输入，输入的值为十进制，其中A为“+”，B为“-”，C为“退格”E为“=”， 4. 数值用数码管以十进制形式显示，以加法为例，初始时显示全“0”，先输入被加数，输入时数字顺序是从左到右。例如，输入1、2、3应该在显示器上上显示“123”，在输入运算符，按下运算符键后，数码管显示全“0”，再输入加数，方法和前面一样，最后按下“=”，数码管显示运算结果 二、扩展部分（30 ） 在基础部分上增加乘法功能，实现两个无符号的4位二进制数的相乘，D为“*”（30 ）-First, the base portion (70 ) to design a simple calculator, it has the following expression: 1. Sum of two unsigned 8-bit binary number subtraction of two unsigned 8-bit binary number values ​ ​ and operators with 44 keyboard input, the input value is decimal, where A is the+ B for " -" C " backspace" E " =" Numerical digital tube In addition, for example, when the initial display of " 0" , the first input is addend input digital sequence is from left to right is displayed in decimal form. For example, enter 1, 2 and 3 on the display should be displayed on the " 123" digital display " 0" , the input operator, press the operator key, and then enter the addend, methods, and as before, and finally press under the " =" , digital display the result of the operation, expansion portion (30 ) increase in the base part multiplication function, the multiplication of two unsigned 4-bit binary number, D is the " *" (
Platform: | Size: 455680 | Author: 孟晓慧 | Hits:

[Other Embeded program] pinlj1

Description: 频率计用51单片机计数器d触发器锁存器组成高精度频率计-Frequency counter with 51 single counter d flip-flop latch constitute precision frequency meter
Platform: | Size: 29696 | Author: li | Hits:

[VHDL-FPGA-Verilog] New folder

Description: verilog codes for counter,d flipflop,fibonacci series,prime numbers,top.
Platform: | Size: 3072 | Author: sanh | Hits:
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