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[Other resource] 脉冲记时CPLD

Description: 工作原理： 脉冲输入，记录30个脉冲的间隔时间（总时间），LED显示出来，牵涉到数码管的轮流点亮，以及LED的码。输入端口一定要用个 74LS14整一下，图上没有。数码管使用共阴数码管。MAXPLUS编译。 测试时将光电门的信号端一块连接到J2口的第三管脚，同时第一管脚为地，应该与光电门的地连接（共地）。 开始测试： 按下按键，应该可以见到LED被点亮，指示可以开始转动转动惯量盘，等遮光片遮挡30次光电门后， LED熄灭，数码管有数字显示，此为时间值，单位为秒，与智能计时器的连续脉冲测试模式中的T30值进行比较。 再按下按键即可进行下一次测量。 水平有限，见笑。-principle : pulse input, recording 30 pulse interval (total time), the LED display and digital control involves rotating lights, and LED yards. Input port must use the entire 000 74LS14 that there is no map. Digital control the use of digital control were overcast. Segments compiler. Test the door to the photoelectric signal an end connected to the mouth of the third J2 pins, for the first pin, should the photoelectric doors to connect (to a total). Testing : press the button, should be able to see the LEDs are lit, instructions to start the rotation inertia set, films such as shading block 30 photoelectric doors, the LED is off, digital possession figures show that for the time value of this unit for seconds Intelligent timer with a continuous pulse mode testing of T30 values were compare
Platform: | Size: 644978 | Author: 高颖峰 | Hits:

[Other resource] cpld(huaqi)

Description: 上海外滩看到的最大的LED显示屏的内核源代码，主要是完成视频信号的远距离传输的编解码与接口转换
Platform: | Size: 484494 | Author: liao | Hits:

[Other resource] cpld

Description: 这是个的VHDL点亮LED的程序，大家一齐分享吧
Platform: | Size: 297879 | Author: ljd20045002 | Hits:

[VHDL-FPGA-Verilog] 脉冲记时CPLD

Description: 工作原理： 脉冲输入，记录30个脉冲的间隔时间（总时间），LED显示出来，牵涉到数码管的轮流点亮，以及LED的码。输入端口一定要用个 74LS14整一下，图上没有。数码管使用共阴数码管。MAXPLUS编译。 测试时将光电门的信号端一块连接到J2口的第三管脚，同时第一管脚为地，应该与光电门的地连接（共地）。 开始测试： 按下按键，应该可以见到LED被点亮，指示可以开始转动转动惯量盘，等遮光片遮挡30次光电门后， LED熄灭，数码管有数字显示，此为时间值，单位为秒，与智能计时器的连续脉冲测试模式中的T30值进行比较。 再按下按键即可进行下一次测量。 水平有限，见笑。-principle : pulse input, recording 30 pulse interval (total time), the LED display and digital control involves rotating lights, and LED yards. Input port must use the entire 000 74LS14 that there is no map. Digital control the use of digital control were overcast. Segments compiler. Test the door to the photoelectric signal an end connected to the mouth of the third J2 pins, for the first pin, should the photoelectric doors to connect (to a total). Testing : press the button, should be able to see the LEDs are lit, instructions to start the rotation inertia set, films such as shading block 30 photoelectric doors, the LED is off, digital possession figures show that for the time value of this unit for seconds Intelligent timer with a continuous pulse mode testing of T30 values were compare
Platform: | Size: 645120 | Author: 高颖峰 | Hits:

[VHDL-FPGA-Verilog] tiaoping

Description: 条屏控制器的CPLD编程,主要完成移位寄存器、编码器和译码器的功能-screen controller CPLD programming, the major shift register, the encoder and decoder functions
Platform: | Size: 410624 | Author: 阿九 | Hits:

[VHDL-FPGA-Verilog] verilogled

Description: cpld-epm7128stc100-10驱动四位LED结果显示1234-cpld- epm7128stc100-10 drive four LED 1234 results
Platform: | Size: 197632 | Author: 章风 | Hits:

[VHDL-FPGA-Verilog] LED

Description: 基于alteraCPLD芯片的VHDL点阵滚动显示源代码-VHDL-based alteraCPLD chip dot matrix rolling display the source code
Platform: | Size: 108544 | Author: 林晋阳 | Hits:

[VHDL-FPGA-Verilog] cpld(huaqi)

Description: 上海外滩看到的最大的LED显示屏的内核源代码，主要是完成视频信号的远距离传输的编解码与接口转换-Shanghai Bund to see the largest LED display in the kernel source code, mainly to complete the long-distance video signal transmission codec conversion and interface
Platform: | Size: 484352 | Author: liao | Hits:

[VHDL-FPGA-Verilog] 7led

Description: dp_xiliux 的 CPLD Verilog设计实验,7个LED演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, 7 LED demo. code test.
Platform: | Size: 91136 | Author: pp | Hits:

[VHDL-FPGA-Verilog] cpld

Description: 这是个的VHDL点亮LED的程序，大家一齐分享吧-This is a LED light up the VHDL procedure, let everyone together to share
Platform: | Size: 297984 | Author: ljd20045002 | Hits:

[Software Engineering] fpga_docu

Description: CPLD/FPGA 入门文档。国内某知名fpga开发商编写的基础教程，共18篇。从使用fpga如何点亮led灯到VGA到8051内核使用方法。如果您是打算学习cpld/fpga，建议先阅读这些文章再选择采购开发板。-CPLD/FPGA entry documents. FPGA developers a well-known domestic basis for the preparation of curricula, a total of 18. From how to use the FPGA to the VGA lit lamp led to the 8051 core to use. If you intend to study cpld/fpga, we suggest that you first read the article and then select the procurement development board.
Platform: | Size: 5509120 | Author: gao | Hits:

[Embeded-SCM Develop] cpldfpga

Description: 《CPLDFPGA嵌入式应用开发技术白金手册》源代码，涉及FPGA/CPLD的各个方面，键盘扫描，LED扫描等简单程序及滤波器等的设计-" CPLDFPGA platinum embedded application development technology handbook" source code, related to FPGA/CPLD all aspects of the keyboard scanning, LED scanning filters, such as simple procedures and design
Platform: | Size: 283648 | Author: 付鋆 | Hits:

[VHDL-FPGA-Verilog] cpld

Description: CPLD VHDL 数码管程序 流水灯程序 时钟程序 -CPLD VHDL program LED lights water clock procedures procedures CPLD VHDL program LED lights process water clock procedures
Platform: | Size: 476160 | Author: 朱工 | Hits:

[Embeded-SCM Develop] deCPLDVHDLshijong

Description: 基于CPLD的VHDL语言数字钟（含秒表）设计 利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试方便、故障率低、修改升级容易等特点。 本设计采用自顶向下、混合输入方式（原理图输入—顶层文件连接和VHDL语言输入—各模块程序设计）实现数字钟的设计、下载和调试。 -CPLD based on the VHDL language digital clock (with stopwatch) design using a chip can be completed in addition to the clock source, buttons, speakers and display (LED) in addition to all functions of digital circuits. All digital logic functions are used in the CPLD device VHDL language. This design has a small and short design cycle (design process to achieve timing simulation), to facilitate debugging, fault rate is low and easy to modify the characteristics of the upgrade. The design uses a top-down, mixed input (input schematic- top-level file access and VHDL language input- the module program design) Design of digital clock, download and debug.
Platform: | Size: 95232 | Author: wuhuisong | Hits:

[VHDL-FPGA-Verilog] 48led

Description: 此软件用的是QuartusII 5.1的环境编写的CPLD内的程序，CPLD用的是EPM7128，实现的功能是对计算机的ISA总线读写操作，计算机通过ISA总线，再通过CPLD，来控制LED的亮和灭-This software is used in the preparation of QuartusII 5.1 environment within the CPLD procedures, CPLD using EPM7128, the function of the realization of the ISA bus on the computer to read and write operation, the computer through the ISA bus, and then through the CPLD, to control the LED' s Liang and poverty
Platform: | Size: 201728 | Author: hujianhua | Hits:

[VHDL-FPGA-Verilog] CPLD

Description: AHDL 编写 的 EPM7218 程序，实现LED控制-EPM7218 prepared AHDL program and achieving LED control
Platform: | Size: 91136 | Author: 李先生 | Hits:

[Software Engineering] colour-LED-CPLD

Description: 一个基于CPLD的彩灯控制器，设计原理及部分代码-CPLD-based Lantern controller, design principles and some of the code
Platform: | Size: 222208 | Author: jackk | Hits:

[VHDL-FPGA-Verilog] s3esk_startup

Description: 利用kcpsm3控制lcd显示 平台：ise 10.1， picoblaze， Spartan3e 开发板 说明：综合按键和lcd、led的功能，思想简单，需要新技术，适合想在fpga方面深造的人。-using kcpsm3 for lcd display platform: ise 10.1， picoblaze， Spartan-3E FPGA Starter Kit Board comment: involve lcd/led/switch, simple mind but need up-to-date technics, suitable for who want to go deep in fpga development.
Platform: | Size: 1106944 | Author: kn | Hits:

[VHDL-FPGA-Verilog] Cymometer

Description: Verilog 编写的频率计，使用8位LED作为显示，Quartus II 6.0的工程文件。保证好用，EPM240T的芯片。使用了66 的资源。-Written in Verilog frequency counter, using 8-bit LED as the display, Quartus II 6.0 of the project file. To ensure easy to use, EPM240T chips. 66 of the resources used.
Platform: | Size: 585728 | Author: 石头 | Hits:

[VHDL-FPGA-Verilog] led

Description: 利用计数器设计延时函数，通过四个led灯的闪烁，可以直观观察延时时长，fpga器件cyclone iv LCMXO2-1200HC-4TG144CR1,在demo板上作简路图(Using the counter to design the delay function, through the flashing of four LED lights, we can observe the delay time directly, FPGA device cyclone IV LCMXO2-1200HC-4TG144CR1, and make the simple path diagram on the demo board)
Platform: | Size: 3163136 | Author: qing wang | Hits:
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