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[VHDL-FPGA-Verilog] cpuTerminate

Description: 用VHDL 编写的一个16位的cpu 设计方案，可以执行8条指令。-use VHDL to prepare a 16 cpu design of the program, the implementation of eight instructions.
Platform: | Size: 2108416 | Author: 宋文强 | Hits:

[VHDL-FPGA-Verilog] cpu-leon3-altera-ep2s60-ddr

Description: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的DDR控制器程序！-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of DDR controller program!
Platform: | Size: 752640 | Author: zhao onely | Hits:

[VHDL-FPGA-Verilog] elock.verilog.pdf

Description: 一种基于Verilog的电子密码锁的论文介绍。有部分程序代码。-Verilog-based electronic locks thesis introduction. Some program code.
Platform: | Size: 294912 | Author: 李里 | Hits:

[VHDL-FPGA-Verilog] minicpu

Description: 一个cpu的vhdl语言程序。非常好的 一个cpu的vhdl语言程序。非常好的-A cpu of the VHDL language program. A very good cpu the VHDL language program. Very good
Platform: | Size: 94208 | Author: hjj | Hits:

[Graph Recognize] lcd-code

Description: 比较完整的LCD接口代码，verilog编写，分为6800和8080两种CPU接口，且有完整的仿真程序-Relatively complete LCD interface code, verilog prepared 6800 and 8080 is divided into two types of CPU interfaces, and there is a complete simulation program
Platform: | Size: 1831936 | Author: 李佳 | Hits:

[Windows Develop] CPU

Description: RC4 Encrpytion 1.Encrpyt strings 2.Create pairs of keys for encoding and decoding automatically 3.Present the crptograph 4.Decode the crptograph to get the plaintext -This CPU has basic instruction set, and we utilize its instruction set to generate a program to verify its performance. Four parts constitute a simple CPU: the control unit, the internal registers, the ALU and instruction set.
Platform: | Size: 34816 | Author: Jane | Hits:

[source in ebook] Chapter1-5

Description: 第一章到第五章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter to Chapter V of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, function authentication, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 1580032 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] Chapter6-9

Description: 第六章到第九章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter VI to Chapter IX of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 6281216 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] Chapter10

Description: 第十章的代码。 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示-Chapter X code. This book by more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of additions device/counters, multipliers/dividers, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and the results demonstrate
Platform: | Size: 6872064 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] Microprogramcontroller

Description: 微程序控制器部件实验，使用VHDL语言使用Quartus测试通过，模拟CPU-Micro-program controller component experiments, the use of VHDL language use Quartus test, simulation CPU
Platform: | Size: 752640 | Author: 糖糖 | Hits:

[assembly language] cpu-poc

Description: 满足并行输出输入的功能，同时与打印机相连，程序中又添加了微处理器的程序。-To meet the parallel input-output function, while with the printer connected to the program has added a microprocessor program.
Platform: | Size: 1736704 | Author: 商客 | Hits:

[assembly language] course-design-cpu-poc

Description: 满足并行输出输入的功能，同时与打印机相连，程序中又添加了微处理器的程序。-To meet the parallel input-output function, while with the printer connected to the program has added a microprocessor program.
Platform: | Size: 1760256 | Author: 商客 | Hits:

[Embeded-SCM Develop] Micro-program

Description: 微程序控制电路是CPU 控制器的核心电路，控制产生指令执行时各部件协调工作所需的所有控制信号，以及下一条指令的地址。微程序控制器的组成如图6-12 所示，主要由三个部分组成，分别是微指令控制电路、微地址寄存器和微指令存储器lpm_rom 其中微指令控制电路用组合电路对指令中的1[7..2] 、操作台控制信号SWA 和SWB 的状态、状态寄存器的输出状态FC 、FZ ，产生微地址变化的控制信号，实现对微地址控制:微地址寄存器控制电路的基本输入信号是微指令存储器的下地址字段M[6..1] ，同时还受微指令控制电路的输出信号SE[6..1]和复位信号RST 的控制，输出下一个微指令的地址:控制存储器由FPGA 中的LPM ROM 构成，输出24 位控制信号。在24 位控制信号中，微命令信号为18 位，微地址信号豆位。在口时刻将打入微地址寄存器UA 的内容，即为下一条微指令地址.当T4时刻进行测试判别时，转移逻辑满足条件后输出的负脉冲，通过强制端将某一触发器置为"1"状态，完成地址修改。微程序控制器中的微控制代码可以通过对FPGA 中LPMß OM 的配置进行输入，通过编辑LPM ROM.mif 文件来修改微控制代码。详细情况可参考LPIÞ CROM的配置方法。微指令控制电路内部结构如图6-2 ， 6-3. 6-13 所示-Micro-program control circuit is the core CPU controller circuit, the control instruction execution produces the coordination of all parts of all the necessary control signals, and the next instruction address. The composition of micro-program controller shown in Figure 6-12, the main three components, namely, microinstruction control circuit, micro-address register and the microcode memory lpm_rom microcode control circuit which combination circuit with instruction in the 1 [ 7 .. 2], SWA and SWB console control signal state, the state register output state FC, FZ, produce changes in micro-address control signals, to realize the micro-address control: micro-address register control circuit input signal is the basic micro- The next address field instruction memory M [6 .. 1], but also by the microcode control circuit output signal SE [6 .. 1] and reset control signal RST, the output of the next microinstruction address: control memory by the FPGA in the LPM ROM form, the output 24-bit
Platform: | Size: 2584576 | Author: 623902748 | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 设计以及基本的CPU，至少包括四个基本单元，控制单元，内部寄存器，ALU和指令集-The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its performance. For simplicity, we will only consider the relationship among the CPU, registers, memory and instruction set. That is to say we only need consider the following items: Read/Write Registers, Read/Write Memory and Execute the instructions. At least four parts constitute a simple CPU: the control unit, the internal registers, the ALU and instruction set, which are the main aspects of our project design and will be studied.
Platform: | Size: 2196480 | Author: mollyma | Hits:

[Other] cpu

Description: 包括1) 时钟发生器 2) 指令寄存器 3) 累加器 4) RISC CPU算术逻辑运算单元 5) 数据控制器 6) 状态控制器 7) 程序计数器 8) 地址多路器 -1) clock generator 2) instruction register 3) accumulator 4) RISC CPU arithmetic logical unit 5) of the data controller 6) state controller 7), the program counter 8) address multiplexer
Platform: | Size: 440320 | Author: liuying | Hits:

[VHDL-FPGA-Verilog] CPU-Project

Description: CPU设计，包含基本的指令集，能执行简单的程序。考虑了CPU，寄存器，存储器和指令集之间的关系。即读写寄存器，读写存储器和执行指令。-CPU design, including basic instruction set, to execute a simple program. Consider the CPU, registers, memory, and the relationship between instruction sets. That read and write registers, read and write memory and execution.
Platform: | Size: 3383296 | Author: ilmf | Hits:

[VHDL-FPGA-Verilog] CPU-exp

Description: 基于VHDL编写的CPU程序，用微程序的方式实现。内含说明本程序的说明文档。-CPU program written in VHDL, with the micro-program ways.Containing the document of the program.
Platform: | Size: 1297408 | Author: gy | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 用VHDL写的一个cpu程序，可以在实验台上运行运行，包括各种基本的寻址方式，里面还含有每个模块的波形-Use VHDL to write a cpu program that can run on the bench run, including a variety of basic addressing modes, which also contains the waveform of each module
Platform: | Size: 2459648 | Author: sherrytonger | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 用VHDL写的一个cpu程序，可以在实验台上运行运行，包括各种基本的寻址方式，里面还含有每个模块的波形-Use VHDL to write a cpu program that can run on the bench run, including a variety of basic addressing modes, which also contains the waveform of each module
Platform: | Size: 2459648 | Author: sherrytonger | Hits:

[Other] VHDL

Description: 用VHDL写的模拟cpu程序，可以下载到硬件完成仿真，东南大学课程设计- Written in VHDL simulation CPU program, you can download to the hardware simulation, Southeast University curriculum design
Platform: | Size: 2678784 | Author: 戴娜 | Hits:
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