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[Driver Develop] MYcy7c68013usbdriver

Description: 本数据包提供基于CY7C68013的开发USB的设备驱动程序代码，-the packet-based development CY7C68013 USB device driver code,
Platform: | Size: 93184 | Author: lcc | Hits:

[VHDL-FPGA-Verilog] cy7c68013fpga

Description: BulkIn是FPGA向CY7C68013发送数据 BulkOut是FPGA从CY7C68013接收数据,可以用LED显示 -BulkIn is the FPGA to the CY7C68013 is BulkOut send data CY7C68013 receive data from the FPGA, you can use LED display
Platform: | Size: 265216 | Author: 简 | Hits:

[VHDL-FPGA-Verilog] CY7c68013_FPGA_Read_Sram

Description: FPGA读SRAM中的数再传给CY7C68013-Reading SRAM in the FPGA, then pass on a few CY7C68013
Platform: | Size: 269312 | Author: 简 | Hits:

[VHDL-FPGA-Verilog] CY7c68013_fpga_write_sram

Description: FPGA将从CY7C68013读到的数写入SRAM-FPGA will read a few CY7C68013 write SRAM
Platform: | Size: 286720 | Author: 简 | Hits:

[SCM] fifo_FPGA

Description: CY7c68013 GPIF程序绝对可用-Procedures can be used absolutely CY7c68013 GPIF
Platform: | Size: 870400 | Author: liwenxin | Hits:

[USB develop] CY7C68013-A

Description: usb 的开发文档，非常有参考价值 详细讲述了CY7C68013的开发过程-usb development documents, a very valuable reference for a detailed account of the development process CY7C68013
Platform: | Size: 1555456 | Author: 孙译 | Hits:

[SCM] CY7C68013AD

Description: 本文件是一个我买的开发板的原理图，型号是:CY7C68013,用ALTIUM或PROTELL DXP打开。-This document is a development board I bought the schematic diagram, model is: CY7C68013, with Altium or opens PROTELL DXP.
Platform: | Size: 65536 | Author: 张智勇 | Hits:

[VHDL-FPGA-Verilog] T3_USB_OUT

Description: cy7c68013向外部发送一个数据 ，发送至fpga，fpga的实例程序 -CY7C68013 to send an external data, sent to the fpga, fpga examples of procedures
Platform: | Size: 876544 | Author: ones | Hits:

[VHDL-FPGA-Verilog] usbin_v1.7

Description: 用于cy7c68013与fpga的从FIFO通讯.版本1.7-For the CY7C68013 and FPGA communications from the FIFO. Version 1.7
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] USB2_0

Description: USB2_0控制器CY7C68013与FPGA接口的VerilogHDL实现.rar-CY7C68013 and FPGA controller USB2_0 interface VerilogHDL achieve. Rar
Platform: | Size: 365568 | Author: fiann | Hits:

[SCM] cy7c63743

Description: CY7C68013单片机通信测试:数据从控制面板传入EP1IN端点，然后送入IOA端口，然后程序读取IOA端口，送入EP1IN端点，在控制面板显示。-CY7C68013 Singlechip communications test: data from the control panel EP1IN incoming endpoint, and then into the IOA port, and then the procedure to read IOA port, into EP1IN endpoint, the control panel display.
Platform: | Size: 601088 | Author: 寒剑 | Hits:

[USB develop] CY7c68013_fpga_write_sram

Description: FPGA自FX2 slavefifo中读取数据，写入至SRAM-FPGA since FX2 slavefifo read data, write to the SRAM
Platform: | Size: 286720 | Author: 郭伟 | Hits:

[VC/MFC] Chap17

Description: VC++ cy7c68013 usb上位机-VC++ cy7c68013 usb PC
Platform: | Size: 1777664 | Author: 凌世波 | Hits:

[VC/MFC] Chap14

Description: VC++ usb cy7c68013 上位机-VC++ usb cy7c68013 PC
Platform: | Size: 161792 | Author: 凌世波 | Hits:

[Program doc] 68013_SlaveFIFO

Description: cy7c68013工作在SLAVE FIFO下的FPGA源代码，已经通过，Verilog编写-cy7c68013 slave fifo mode code ,written by hard ware language
Platform: | Size: 2151424 | Author: 杨瑞 | Hits:

[Other] 68013

Description: 介绍了此控制器与FPGA接口的控制和HDL (硬件描述语言)实现方法。利用CY7C68013控制器的 Slave F IFO从机方式,用Verilog HDL在FPGA中产生相应的控制信号,实现对数据的快速读写。试验 结果表明此方案传输速度快、数据准确,可扩展到其他需要通过USB进行快速数据传输的系统中-This paper describes the controller and the FPGA interface to control and HDL (hardware description language) implementations. Use CY7C68013 controller Slave F IFO slave mode, using Verilog HDL in the FPGA generate a corresponding control signal to achieve fast read and write data. The results show that this program transmission speed, accurate data can be expanded to other needs through the USB for fast data transfer system
Platform: | Size: 365568 | Author: 余岳衡 | Hits:

[Books] usb

Description: 在高速的数据采集或传输中，目前使用较多的都是采用USB 2．0接口控制器和FPGA或DSP实现的，本设计在USB 2．0接口芯片CY7C68013的Slave FIFO模式下，利用FPGA作为外部主控制器实现对FX2 USB内部的FIFO进行控制，以实现数据的高速传输。该模块可普遍适用于基于USB 2．0接口的高速数据传输或采集中。-In the high-speed data acquisition or transmission, the currently used are based on more USB 2.0 interface controller and the FPGA or DSP implementation, the design USB 2.0 interface chip CY7C68013 of the Slave FIFO mode, the use of FPGA as a the external FX2 USB host controller to realize the internal FIFO control, in order to achieve high-speed data transmission. The module can be generally applied based on high-speed USB 2.0 interface, transfer or acquisition of data.
Platform: | Size: 894976 | Author: jiang_jennifer | Hits:

[VHDL-FPGA-Verilog] CY7C68013

Description: USB2.0的Verilog实现，含有完整的FPGA代码-Use Verilog to implement the USB2.0 protcol
Platform: | Size: 600064 | Author: XCP | Hits:

[VHDL-FPGA-Verilog] USB20develop

Description: cy7c68013结合FPGA的开发笔记，本人原创，FPGA平台是DE2-cy7c68013+fpga develop note
Platform: | Size: 414720 | Author: caizuhong | Hits:

[VHDL-FPGA-Verilog] CY7C68013固件程序 FPGA测试Verilog程序

Description: CY7C68013固件程序 FPGA测试Verilog程序(CY7C68013 firmware, FPGA test, Verilog)
Platform: | Size: 198656 | Author: regan_wang | Hits:
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