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[Other resource] my_dcm

Description: 在xilinx的ISE环境中配置一个DCM组件，可进行查看程序运行的时间。通过串口与终端设备相连
Platform: | Size: 710456 | Author: 张杰 | Hits:

[Documents] ise

Description: xilinx的时序约束实验，通过阅读本文档，你可以用全局时序约束来轻松提高已有的项目的系统时钟频率，同时你还可以用映射后静态时序报告以及布局布线后静态时序报告来分析你的设计性能-Xilinx timing constraints of the experiment, by reading this document, you can use the overall timing constraints to easily enhance existing projects the system clock frequency, at the same time you can also use static timing report after mapping, as well as after placement and routing static timing analysis report to you design performance
Platform: | Size: 271360 | Author: 江巧微 | Hits:

[VHDL-FPGA-Verilog] my_dcm

Description: 在xilinx的ISE环境中配置一个DCM组件，可进行查看程序运行的时间。通过串口与终端设备相连-In the Xilinx ISE environment, configure a DCM components, can view the program is running time. Through the serial port and terminal equipment connected to
Platform: | Size: 710656 | Author: 张杰 | Hits:

[VHDL-FPGA-Verilog] dcm2

Description: 基于Xilinx Vertex4的可综合的二级DCM模块源代码，可生成400Mhz时钟信号-Based on Xilinx Vertex4 of two integrated DCM module source code, can generate 400Mhz clock signal
Platform: | Size: 1024 | Author: 云 | Hits:

[Other] DCM

Description: 关于dcm的教材。教你如何使用dcm。非常值得一看哦-Materials on the DCM. Teach you how to use the dcm. Oh, very much worth a visit
Platform: | Size: 621568 | Author: 刘峰 | Hits:

[VHDL-FPGA-Verilog] BUFG_CLK2X_FB_SUBM

Description: xilinx DCM 应用的源代码，完全可用-xilinx DCM application source code, fully available
Platform: | Size: 1024 | Author: 娃娃 | Hits:

[VHDL-FPGA-Verilog] BUFG_CLK0_FB_SUBM

Description: xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
Platform: | Size: 1024 | Author: 娃娃 | Hits:

[VHDL-FPGA-Verilog] BUFG_CLK0_SUBM

Description: xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
Platform: | Size: 1024 | Author: 娃娃 | Hits:

[VHDL-FPGA-Verilog] BUFG_CLK2X_SUBM

Description: xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
Platform: | Size: 1024 | Author: 娃娃 | Hits:

[VHDL-FPGA-Verilog] BUFG_CLKDV_SUBM

Description: xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
Platform: | Size: 1024 | Author: 娃娃 | Hits:

[Documents] DCM

Description: Xilinx公司诸多型号开发版中的一个模块，能够实现1到16次倍频和分频等功能。使用时现在ISE集成开发环境下利用VHDL进行例化。本文档为个人学习总结-Xilinx, a number of models developed version of a module, be able to achieve 1-16 times multiplier and divider functions. ISE now use integrated development environment for the use of VHDL-based cases. This document for personal study and summary
Platform: | Size: 163840 | Author: 张潘睿 | Hits:

[VHDL-FPGA-Verilog] DCM_12M_1M

Description: xilinx下DCM输出12Mhz和1Mhz-Verilog DCM xilinx ISE
Platform: | Size: 1024 | Author: fpgabo | Hits:

[VHDL-FPGA-Verilog] Xilinx_DCM

Description: 基于ise 10.0来实现Xilinx的时钟设计和管理-Xilinx dcm digital clock manager
Platform: | Size: 8192 | Author: ise_dcm | Hits:

[VHDL-FPGA-Verilog] ISE_lab15

Description: 利用XILINX官方例程熟悉PicoBlaze软核；熟悉使用Architecture Wizard配置和初始 化DCM；掌握使用核生成器（Core Generate）生成一个IP核，并将其插入到设计中。-XILINX official familiar with the routine use of soft-core PicoBlaze familiar with the Architecture Wizard configuration and initialization DCM master the use of nuclear generators (Core Generate) to generate a IP core, and insert it into the design.
Platform: | Size: 2069504 | Author: zhangsheng | Hits:

[VHDL-FPGA-Verilog] dcm

Description: Xilinx的V4FPGA数字时钟管理模块的底层原语实现代码，硬件上跑通- The Xilinx V4FPGA digital clock administration module s first floor primitive realizes the code, on the hardware runs passes
Platform: | Size: 1263616 | Author: 许磊 | Hits:

[VHDL-FPGA-Verilog] DCM

Description: xilinx SP605开发板的DCM模块验证程序，coreGen工具生成DCM核，由DCM完成时钟分频、倍频、移相等操作-xilinx SP605 development board DCM module validation program, coreGen tool to generate nuclear DCM, completed by the DCM clock divider, frequency, and shift operations equal
Platform: | Size: 2599936 | Author: wangyu | Hits:

[VHDL-FPGA-Verilog] double_dcm

Description: 这个主要是在xilinx FPGA中双DCM连接的问题，这个问题网上资料很少，自己研究后并且仿真之后可以实现两个dcm的正常工作，实现倍频和时钟的反相-This is mainly the double in xilinx FPGA DCM connection problem which little information online, their own studies and simulation can be achieved after the normal work of the two dcm achieve clock frequency and the inverse
Platform: | Size: 80896 | Author: 张元甲 | Hits:

[VHDL-FPGA-Verilog] ddr_100Mhz_2011.03.12

Description: 这个工程是用xilinx的MIG生成的对于spartan 3E的实验板的ddr的控制器，我已经能够在上面修改之后加入自己的思想，包括两个dcm的模块。-This project is the MIG generated by xilinx spartan 3E development board for the ddr controller, I have been able to modify the above by adding his own ideas, including the two dcm module.
Platform: | Size: 6132736 | Author: 张元甲 | Hits:

[VHDL-FPGA-Verilog] DCM

Description: 详细介绍了基于XILINX公司FPGA时钟管理模块DCM的IP核生成和使用-xilinx ise DCM
Platform: | Size: 621568 | Author: mawei | Hits:

[VHDL-FPGA-Verilog] dcm_test2

Description: xilinx fpga 倍频的例子，包含整个工程， 如果去用ISE 实现倍频，dcm 用法-xilinx s FPGA dcm example
Platform: | Size: 315392 | Author: 林端 | Hits:
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