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[VHDL-FPGA-Verilog] ref-ddr-sdram-vhdl DL : 0: 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
Update : 2025-02-17 Size : 1007kb Publisher : 包盛花
[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl DL : 0: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Update : 2025-02-17 Size : 758kb Publisher : 张涛
[VHDL-FPGA-Verilog] ddr DL : 0: 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
Update : 2025-02-17 Size : 2kb Publisher : 孙强
[VHDL-FPGA-Verilog] ddr_sdram_controller_vhdl DL : 0: ddr_sdram控制器的vhdl代码,里面的地址和数据长度可配置,能满足不同用户的需要.-ddr_sdram controller vhdl code, which addresses and the data length can be configured, meet the needs of different users.
Update : 2025-02-17 Size : 13kb Publisher : hxwf801
[Other] ref-ddr-sdram-vhdl DL : 0: 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
Update : 2025-02-17 Size : 427kb Publisher : kevin
[Documents] SDRAM-VHDL DL : 0: SDRAM控制器的VHDL实现，pdf格式，有需要多的，联系我-SDRAM controller VHDL, pdf format, it needs more, Contact
Update : 2025-02-17 Size : 122kb Publisher :
[VHDL-FPGA-Verilog] cpu-leon3-altera-ep2s60-ddr DL : 0: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的DDR控制器程序！-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of DDR controller program!
Update : 2025-02-17 Size : 735kb Publisher : zhao onely
[VHDL-FPGA-Verilog] cntl_ddr3(xilinx) DL : 0: xilinx ddr3最新VHDL代码,通过调试-xilinx ddr3 latest VHDL code through debugging
Update : 2025-02-17 Size : 99kb Publisher : zhang chi
[VHDL-FPGA-Verilog] DDR2_module_VHDL_test(Rev0.1) DL : 0: ddr 2 接口读写测试模块 ddr 2 接口读写测试模块 -ddr 2 interface test module ddr 2 read and write interface to read and write test module
Update : 2025-02-17 Size : 123kb Publisher : 骑士
[Other] ddr_ctrlv DL : 0: ddr ram controller vhdl code
Update : 2025-02-17 Size : 54kb Publisher : heyong
[VHDL-FPGA-Verilog] rtl DL : 0: DDR控制器已通过FPGA 验证大家不要错过哦-DDR controller has passed FPGA to verify that we will not miss Oh
Update : 2025-02-17 Size : 51kb Publisher : kin
[VHDL-FPGA-Verilog] DDR_SDRAM_controller DL : 0: ddr sdram 的vhdl实现，包括各个模块的实现以及仿真文件-ddr sdram realization of VHDL, including the realization of each module as well as the simulation file
Update : 2025-02-17 Size : 998kb Publisher : shroy
[VHDL-FPGA-Verilog] ref-ddr-sdram-vhdl DL : 0: 基于VHDL编写的DDR-SDRAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the DDR-SDRAM controller programming, is currently the industry s commonly used RAM controller
Update : 2025-02-17 Size : 1007kb Publisher : wfs
[Other] testbench DL : 0: ddr sdram controller datd module source code
Update : 2025-02-17 Size : 3kb Publisher : KrishnaKishore
[VHDL-FPGA-Verilog] DDR_SDRAM DL : 0: DDR RAM控制器的VHDL源码, 实现平台是Lattice FPGA-DDR RAM controller VHDL source code, the realization of Lattice FPGA platform is
Update : 2025-02-17 Size : 661kb Publisher : 黄达
[VHDL-FPGA-Verilog] 03.EDK8.2 DL : 0: 使用xilinx virtex4芯片，设计环境为EDK，其中包含uart,片外sram操作，flash操作，DDR SDRAM操作，MAC自发自收，audio，video等试验-Xilinx virtex4 use chip design environment for the EDK, which contains the uart, chip sram operation, flash operation, DDR SDRAM operation, MAC spontaneous self-admission, audio, video and other tests
Update : 2025-02-17 Size : 21.76mb Publisher : 肖姗姗
[VHDL-FPGA-Verilog] DDRctroll DL : 0: ddr 的fpga 控制器的实现仿真正确-ddr controller fpga to achieve the correct simulation
Update : 2025-02-17 Size : 3.79mb Publisher : gongranli
[VHDL-FPGA-Verilog] c_xapp851 DL : 1: 这是xilinx应用指南xapp851的中文版本。本应用指南描述了在 Virtex™ -5 器件中实现的 200 MHz DDR SDRAM （JEDEC DDR400 (PC3200) 标准）控制器。本设计实现使用 IDELAY 单元调整读数据时序。读数据时序校准和调整在此控制器中完成。-This is the xilinx application note xapp851 the Chinese version. This application note describes the Virtex ™ -5 devices to achieve 200 MHz DDR SDRAM (JEDEC DDR400 (PC3200) standard) controller. The Design and Implementation of the use of IDELAY unit to adjust read data timing. Reading the data calibration and adjust the timing for completion of this controller.
Update : 2025-02-17 Size : 399kb Publisher : 陈阳
[Software Engineering] DDR2_hardcore_userguide DL : 0: xillinx Spartan6 FPGA DDR 接口设计指南-xillinx Spartan6 FPGA DDR Interface Design Guidelines
Update : 2025-02-17 Size : 2.22mb Publisher : james
[VHDL-FPGA-Verilog] ddr-sdram--chengxu DL : 0: ddr的控制程序，实用Verilog语言实现的非常的具体，非常无奈过的实用。-ddr
Update : 2025-02-17 Size : 14kb Publisher : 张杰

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