Search - ddr_sdram

[Other resource] ddr_verilog_xilinx

Description: 该程序是在xilinx的FPGA上实现DDR_SDRAM接口，程序是用verylog语言写的-that the procedure was in Xilinx FPGA to achieve DDR_SDRAM interface, procedures used to write the language verylog
Platform: | Size: 23407 | Author: 冯伟 | Hits:

[Other resource] ddr_sdram_controller_vhdl

Description: ddr_sdram控制器的vhdl代码,里面的地址和数据长度可配置,能满足不同用户的需要.-ddr_sdram controller vhdl code, which addresses and the data length can be configured, meet the needs of different users.
Platform: | Size: 13983 | Author: hxwf801 | Hits:

[Other resource] !ddr_sdram

Description: ddr sram的官方文档,介绍了ddr sram的使用及其接口等各方面的消息资料.
Platform: | Size: 452448 | Author: wang | Hits:

[Software Engineering] DDR_SDRAM

Description: 该项对于设计DDSRAM有很大的帮助，希望可以对你有所帮助。
Platform: | Size: 474492 | Author: 王辉 | Hits:

[SourceCode] ddr_sdram

Description: ddr_sdram的控制程序，希望有用。
Platform: | Size: 13753 | Author: arklau | Hits:

[VHDL-FPGA-Verilog] ddr_verilog_xilinx

Description: 该程序是在xilinx的FPGA上实现DDR_SDRAM接口，程序是用verylog语言写的-that the procedure was in Xilinx FPGA to achieve DDR_SDRAM interface, procedures used to write the language verylog
Platform: | Size: 23552 | Author: 冯伟 | Hits:

[VHDL-FPGA-Verilog] ddr_sdram_controller_vhdl

Description: ddr_sdram控制器的vhdl代码,里面的地址和数据长度可配置,能满足不同用户的需要.-ddr_sdram controller vhdl code, which addresses and the data length can be configured, meet the needs of different users.
Platform: | Size: 13312 | Author: hxwf801 | Hits:

[Other] !ddr_sdram

Description: ddr sram的官方文档,介绍了ddr sram的使用及其接口等各方面的消息资料.-ddr sram official documents, ddr sram introduced the use of its interface and other sources of information.
Platform: | Size: 452608 | Author: wang | Hits:

[Software Engineering] DDR_SDRAM

Description: 该项对于设计DDSRAM有很大的帮助，希望可以对你有所帮助。-For the design of the DDSRAM have great help, I hope you can help.
Platform: | Size: 474112 | Author: 王辉 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM

Description: 利用fpga读写ddr的源代码实测可以使用-Ddr use FPGA to read and write the source code can use the measured
Platform: | Size: 474112 | Author: 朱宝军 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM

Description: DDR RAM控制器的VHDL源码, 实现平台是Lattice FPGA-DDR RAM controller VHDL source code, the realization of Lattice FPGA platform is
Platform: | Size: 676864 | Author: 黄达 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM

Description: DDR——SDRAM学习资料，DDR——SDRAM学习资料-DDR- SDRAM learning materials, DDR- SDRAM learning materials
Platform: | Size: 338944 | Author: ytqcom | Hits:

[VHDL-FPGA-Verilog] ref-ddr-sdram-verilog

Description: ddr_sdram开发参考verilog建模-ddr_sdram with verilog
Platform: | Size: 753664 | Author: pengyong | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM

Description: ddr sdram 的控制程序，lattice的，比较好用的，大家-ddr sdram control program, lattice, and relatively easy to use, and we look
Platform: | Size: 8483840 | Author: 熊熊 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM

Description: SDRAM控制器的相关源程序代码有需要的同学可以下载-SDRAM controller source code related to students in need can be downloaded
Platform: | Size: 24576 | Author: 安圣基 | Hits:

[VHDL-FPGA-Verilog] DDR-SRAM

Description: 自己汇总的一些Verilog HDL语言编写的，关于DDR_SDRAM的程序-Verilog HDL DDR_SDRAM
Platform: | Size: 19456 | Author: duwenjian | Hits:

[VHDL-FPGA-Verilog] ddr_sdram

Description: 对ddrsdram操作，用VHDL语言实现，read，write的接口电路控制-Erase operation to read and write on the ddrsdram
Platform: | Size: 3072 | Author: 王伯祥 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM

Description: DDR_SDRAM的fpga实现，内有编写文档及代码，适合FPGA进阶的同学参考学习-DDR_SDRAM fpga implementation, documentation and code written inside, suitable for those students to learn advanced FPGA
Platform: | Size: 361472 | Author: uodsi | Hits:

[VHDL-FPGA-Verilog] ddr_sdram

Description: 包含ddr_sdr_conf_pkg.vhd，reset.vhd，ddr_dcm.vhd，user_if.vhd，ddr_sdram.vhd，Mt46v16m16.vhd以及仿真TB文件；设计采用Virtex ii系列芯片，DDR_SDRAM型号为Mt46v16m16，可用于进行DDR控制的初步学习使用；通过细致了解并进行逻辑控制，可深入理解DDR芯片内部构造；支持133MHz系统时钟频率，突发长度为2，可进行读、写、NOP、激活、自刷新配置、预充电以及各ROW/BANK的激活改变等动作，较适合DDR入门使用(Including the ddr_sdr_conf_pkg.vhd, reset.vhd, ddr_dcm.vhd, user_if.vhd, ddr_sdram.vhd, Mt46v16m16.vhd and simulation TB files; designed with Virtex ii series chips, DDR_SDRAM model for the Mt46v16m16, can be used for initial control of DDR control ; Through careful understanding and logic control, in-depth understanding of DDR chip internal structure; Support 133MHz system clock frequency, burst length of 2, can be read, write, NOP, activation, self-refresh configuration, pre-charge and the activation of the ROW / BANK change action, more suitable for DDR entry)
Platform: | Size: 20480 | Author: 唛侬 | Hits:

[VHDL-FPGA-Verilog] DDR_sdram

Description: 文件里有DDR3/DDR4 sram的verliog模型，而且具有DDR4参考书(The document has a verliog model of DDR3/DDR4 SRAM, and it has DDR4 reference books.)
Platform: | Size: 4935680 | Author: maxw123456789 | Hits:

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[Other resource] ddr_verilog_xilinx

[Other resource] ddr_sdram_controller_vhdl

[Other resource] !ddr_sdram

[Software Engineering] DDR_SDRAM

[SourceCode] ddr_sdram

[VHDL-FPGA-Verilog] ddr_verilog_xilinx

[VHDL-FPGA-Verilog] ddr_sdram_controller_vhdl

[Other] !ddr_sdram

[Software Engineering] DDR_SDRAM

[VHDL-FPGA-Verilog] DDR_SDRAM

[VHDL-FPGA-Verilog] DDR_SDRAM

[VHDL-FPGA-Verilog] DDR_SDRAM

[VHDL-FPGA-Verilog] ref-ddr-sdram-verilog

[VHDL-FPGA-Verilog] DDR_SDRAM

[VHDL-FPGA-Verilog] DDR_SDRAM

[VHDL-FPGA-Verilog] DDR-SRAM

[VHDL-FPGA-Verilog] ddr_sdram

[VHDL-FPGA-Verilog] DDR_SDRAM

[VHDL-FPGA-Verilog] ddr_sdram

[VHDL-FPGA-Verilog] DDR_sdram

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