Search - de2-70 lcd display

[VHDL-FPGA-Verilog] DE2_LCM_CCD

Description: 在altera DE2 的开发板上采集图像，到lcd显示的原程序。-In altera DE2 development board collecting images, lcd display to the original procedure.
Platform: | Size: 3439616 | Author: alison | Hits:

[VHDL-FPGA-Verilog] DE2_70_TV

Description: --- --- --- -Verilog--- --- ---- This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor. Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.--------------------Verilog---------------- This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor. Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.
Platform: | Size: 168960 | Author: Sami | Hits:

[VHDL-FPGA-Verilog] ourdev_247126

Description: his design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor. Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize. Running the Design-his design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor. Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize. Running the Design
Platform: | Size: 161792 | Author: 路啄米 | Hits:

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[VHDL-FPGA-Verilog] DE2_LCM_CCD

[VHDL-FPGA-Verilog] DE2_70_TV

[VHDL-FPGA-Verilog] ourdev_247126

[VHDL-FPGA-Verilog] main_control

[VHDL-FPGA-Verilog] clock-a-stopwatch

[Other Embeded program] Character_LCD

[VHDL-FPGA-Verilog] my_example

[VHDL-FPGA-Verilog] SOPC_LCD

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