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[ARM-PowerPC-ColdFire-MIPS] embedded_risc

Description: 一个嵌入式RISC CPU 的Verilog 设计源码，可综合。内含详细的设计文挡。-an embedded RISC CPU design Verilog source code can be integrated. Detailed design containing the text block.
Platform: | Size: 128000 | Author: 箫勇天 | Hits:

[VHDL-FPGA-Verilog] LC3-VHDL-another

Description: 另一套LC3 CPU VHDL源码及设计文档，对LC3进行了一些取舍和改造，比如NZP改为NZC，更贴近现实CPU硬件架构。按照ASM进行VHDL编码，更适合数字设计初学者学习。-Another set of LC3 CPU VHDL source code and design documents, of LC3 to a number of trade-offs and transformation, such as NZP changed NZC, more close to reality CPU hardware architecture. In accordance with the ASM to VHDL coding, digital design more suitable for beginners to learn.
Platform: | Size: 808960 | Author: guo | Hits:

[VHDL-FPGA-Verilog] verilog_design_a_simple_cpu

Description: 用verilog设计一个简单的cpu系统-Verilog design with a simple cpu system
Platform: | Size: 730112 | Author: jiangp | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 多周期CPU设计，使用Verilog HDL语言编程，实现MIPS的指令系统。-CPU design with verilog hdl language.Instructions from MIPS.Something in detial is not perfect.
Platform: | Size: 5579776 | Author: Po | Hits:

[VHDL-FPGA-Verilog] MulticlockCPU.tar

Description: verilog hdl实现多周期CPU，按照有限状态己设计，含源码、实验报告和详细vsd电路图-verilog hdl multi-cycle CPU, in accordance with the finite-state has been the design, including source code, test reports and detailed schematic vsd
Platform: | Size: 19317760 | Author: czl | Hits:

[VHDL-FPGA-Verilog] NET2

Description: This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, using Veril Verilog language, a hardware-base FPGA embedded project combat, Man Application FPGA, FPGA-chip hardw Mallat implementation of wavelet Layer of one-dimensional wavelet
Platform: | Size: 1852416 | Author: sansfroid | Hits:

[VHDL-FPGA-Verilog] Verilog-HDLTOP-DOWN

Description: 用Verilog HDL的建模来设计一个经简化的只有八条指令、字长为一字节的RISC中央处理单元（CPU）的顶层设计。-Modeling with the Verilog HDL to design a simplified and only eight instructions, word length is a byte RISC central processing unit (CPU) of the top-level design.
Platform: | Size: 43008 | Author: 刘鹏飞 | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 一个简单的CPU设计，支持add，sub，mvi，mv四条指令，用Verilog语言编写，在Quratus II上编译通过，仿真正确。-A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.
Platform: | Size: 931840 | Author: 姜涛 | Hits:

[VHDL-FPGA-Verilog] cpu_verilog_vhdl

Description: CPU核verilog、VHDL实现（两个8051带文档 ， or12000 ） 以及cpu设计教程-Personal collection of the CPU core (with two 8051 documents, or12000) plus cpu design tutorials
Platform: | Size: 6079488 | Author: 王垚 | Hits:

[Other] Verilog

Description: 程序员利用一种由专家设计的既可以被人理解，也可以被计算机解释的语言来表示算法问 题的求解过程。这种语言就是编程语言。由它所表达的算法问题的求解过程就是程序。我 们已经熟悉通过编写程序来解决计算问题， C、Pascal、Fortran、Basic 或汇编语言语言 是几种常用的编程语言。如果我们只研究算法，只在通用的计算机上运行程序或利用通用 的CPU 来设计专用的微处理器嵌入系统，掌握上述语言就足够了。如果还需要设计和制造 能进行快速计算的硬线逻辑专用电路，我们必须学习数字电路的基本知识和硬件描述语言。 因为现代复杂数字逻辑系统的设计都是借助于EDA 工具完成的，无论电路系统的仿真和综 合都需要掌握硬件描述语言。在本书中我们将要比较详细地介绍Verilog 硬件描述语言。-Programmers to take advantage of a design by the experts can either be understood algorithmic problem solving process can also be explained by the computer language to represent. This language is a programming language. By it expressed algorithmic problem solving process is the program. We are already familiar with to solve computational problems by writing programs in C, Pascal, Fortran, Basic or assembly language language several common programming languages. If we only study the algorithm, running on a general purpose computer program to design a dedicated microprocessor embedded systems or the use of general-purpose CPU master the above language is sufficient. If you need to design and manufacturing for quick calculation of the hard-wired logic circuit, we must learn the basic knowledge of digital circuit hardware description language. Because the design of the modern complex digital logic systems are accomplished by means of EDA tools, regardless of the circuit system simulation a
Platform: | Size: 1346560 | Author: exia_dl | Hits:

[VHDL-FPGA-Verilog] System-Verilog-and-HDL-skills

Description: 这个教程讲了如何用SystemVerilog写一个CPU，这个教程是和视频专辑http://i.youku.com/u/UMTExNzExOTgw/videos一起使用的，而且里面讲了一些FPGA的逻辑设计技巧-This tutorial about how to use SystemVerilog write a CPU, this tutorial is used in conjunction with, and the video album http://i.youku.com/u/UMTExNzExOTgw/videos and tells about some of FPGA logic design techniques
Platform: | Size: 3183616 | Author: 易瑜 | Hits:

[VHDL-FPGA-Verilog] SC_CPU

Description: single cycle CPU element design with Verilog
Platform: | Size: 14318592 | Author: Virgil | Hits:

[Software Engineering] lab-1-ALU-design-with-Verilog-HDL

Description: cpu设计的运算器部分verilog代码，实验资料，包括原理和代码，在modelsim仿真通过-CPU design arithmetic unit part of the verilog code, experimental data, including the principle and code, through the modelsim simulation
Platform: | Size: 19456 | Author: 张明明 | Hits:

[Software Engineering] lab-4-cpu-design-with-Verilog-HDL

Description: 用veriloghdl 编写的cpu代码，modusim仿真通过，包括原理图和代码，以实验报告形式写出-CPU code, written in veriloghdl modusim simulation through, including the principle diagram and code, in the form of a lab report write
Platform: | Size: 22528 | Author: 张明明 | Hits:

[File Format] CPU

Description: 基于FPGA控制的ASIC CPU系统设计，全是用VERILOG代码编写，可以做加减乘除运算 -FPGA-based control ASIC CPU system design, all made with VERILOG code writing, arithmetic operations can be done
Platform: | Size: 1844224 | Author: xiaokai | Hits:

[ARM-PowerPC-ColdFire-MIPS] OpenMIPS_VerilogHDL_Study_v1.1

Description: 10天用verilog实现MIPS_cpu，内有清晰结构图。很好的cpu设计学习资料！-10 days with verilog achieve MIPS_cpu, within a clear structure diagram. Good cpu design learning materials!
Platform: | Size: 440320 | Author: zyy | Hits:

[VHDL-FPGA-Verilog] cpu_1

Description: 用verilog设计五级CPU的框架，需要自己另行补充指令，可作为学生作业和训练内容-Five CPU with verilog design framework, needs its own separate supplemental instruction can be used as student assignments and training content
Platform: | Size: 1024 | Author: 陈谋奇 | Hits:

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