Description: 数据库课程设计
基于C/S模式的图书管理系统的设计
本文介绍了一个基于Client/Server模式的高校图书管理系统的设计与实现。运用Visual Basic.Net结合Microsoft SQL Server 2000开发的登录模块主要用于验证用户身份，进行有效的操作。从主界面模块在验证后进入每个子模块进行各个子系统的具体功能操作。在整个系统设计中充分利用了模块化的设计思想和开发方法。-database design courses based on the C / S mode of library management system design is based on an m Memory Stick ent / Server model of college library management system design and implementation. Visual basic.Net with Microsoft SQL Server 200 0 logged in the development of the module is used to validate the identity of the owner to carry out effective operation. From the main interface module after verification in each sub-module into the various subsystems for the specific function operation. In the entire system design full advantage of the modular design and development methods. Platform: |
Size: 412731 |
Author:thocr |
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Description: 本文介绍了一个基于Client/Server模式的高校图书管理系统的设计与实现。运用Visual Basic.Net结合Microsoft SQL Server 2000开发的登录模块主要用于验证用户身份，进行有效的操作。从主界面模块在验证后进入每个子模块进行各个子系统的具体功能操作。在整个系统设计中充分利用了模块化的设计思想和开发方法-this paper based on a Client / Server model of the college library management system design and Implementation. Visual basic.Net with Microsoft SQL Server 200 0 logged in the development of the module is used to validate the identity of the owner to carry out effective operation. From the main interface module after verification in each sub-module into the various subsystems for the specific function operation. In the entire system design full advantage of the modular design and development methods Platform: |
Size: 412579 |
Author:孙震 |
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Description: Design and Test_Verilog HDL——EDA先锋工作室《设计与验证—Verilog HDL》配书源代码，很多使用的实例，并有说明，是学习Verilog 不可多得的好资料。-Design and Test_Verilog HDL- EDA pioneer studio design and verification-Verilog HDL book with source code, many examples and has made it clear that it is rare to learn Verilog good information. Platform: |
Size: 1887232 |
Author:ZY |
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Description: Testbenches have become an integral part of the design process, enabling you to verify that
your HDL model is sufficiently tested before implementing your design and helping you automate
the design verification process. It is essential, therefore, that you have confidence your
testbench is thoroughly exercising your design. Collecting code coverage statistics during simulation
helps to ensure the quality and thoroughness of your tests.-Testbenches have become an integral part of the design process, enabling you to verify thatyour HDL model is sufficiently tested before implementing your design and helping you automatethe design verification process. It is essential, therefore, that you have confidence yourtestbench is thoroughly exercising your design. Collecting code coverage statistics during simulationhelps to ensure the quality and thoroughness of your tests. Platform: |
Size: 258048 |
Author:daniel |
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Description: Prentice Design Verification With E ,关于specman/e的好书。-Prentice Design Verification With E, on specman/e books. Platform: |
Size: 1904640 |
Author:downloader |
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Description: Programs in the irregular grid design package described in this manual are used to carry out five main functions:
verification and adjustment of coastline and bathymetric data
preparation of an irregular triangular depth grid covering the domain to be modelled
production of a preliminary irregular triangular model grid with nodes suitably positioned for accurate and efficient numerical modelling
interactive checking and editing, including trimming and joining, of model grid
display and plotting of model output. Platform: |
Size: 944128 |
Author:baobo |
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Description: 设计带进位算术逻辑运算单元，根据74LS181功能表，用Verilog HDL硬件描述语言编程实现ALU181的算术逻辑运算功能，编辑实验原理图，在算术逻辑单元原理图上，将其扩展为带进位的算术逻辑运算单元，对其进行编译，并设计波形对其进行仿真验证，最后下载验证-Design into the digital arithmetic logic operation unit, in accordance with menu 74LS181 with Verilog HDL hardware description language programming ALU181 function arithmetic logic operations, editing Experimental schematic diagram, in the Arithmetic Logic Unit schematic diagram on its expansion into the spaces for arithmetic logic operation unit, its compiler, and the design of their simulation waveforms, and finally download the verification Platform: |
Size: 667648 |
Author:623902748 |
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Description: Advanced Xilinx FPGA
Design with ISE
Objectives
Describe Virtex™ -II advanced architectural features and how they can be used to
improve performance
• Create and integrate cores into your design flow using the CORE Generator™ System
• Describe the different ISE options available and how they can be used to improve
performance
• Describe a flow for obtaining timing closure with Advance Timing Constraints
• Use FloorPlanner to improve timing
• Reduce implementation time with Incremental Design Techniques and Modular Design
Techniques
• Reduce debugging time with FPGA Editor
• On-Chip Verification with ChipScope Pro-Advanced Xilinx FPGA
Design with ISE
Objectives
Describe Virtex™ -II advanced architectural features and how they can be used to
improve performance
• Create and integrate cores into your design flow using the CORE Generator™ System
• Describe the different ISE options available and how they can be used to improve
performance
• Describe a flow for obtaining timing closure with Advance Timing Constraints
• Use FloorPlanner to improve timing
• Reduce implementation time with Incremental Design Techniques and Modular Design
Techniques
• Reduce debugging time with FPGA Editor
• On-Chip Verification with ChipScope Pro Platform: |
Size: 10615808 |
Author:rakesh |
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Description: 要求是：题目内容]
1.计算包含三个运算量和两个运算符的四则运算（形如A+B*C）
2.输入运算量和运算符，计算出结果（对错误的计算式给出提示）
3.可选择连续计算多个计算式
4.是否正确实现题目要求
5.在项目报将以上每一步骤的结果均打印输出，验证程序告中画出程序流程图，说明程序设计的算法，附主要程序段。
6.在项目报告中说明知识点、程序设计过程中的难点、解决办法及编程小结或体会。
-Requirements are: Title Content] 1. Calculation of the amount consists of three operations and two operators of four operations (of the form A+ B* C) 2. Enter the computation and operators to calculate the results (of the wrong formula to the prompt) 3. select multiple consecutive calculation formula 4. to achieve the correct title requirements 5. in the project each step of the above reported results are printed out, tell the verification process to draw flowchart to illustrate the program design algorithm, with the main block. 6. In the project report that knowledge point, the program design process, the difficulties, solutions and program summary or experience. Platform: |
Size: 3072 |
Author:孙玉花 |
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Description: In the semiconductor and electronic design industry, Verilog is a hardware description language (HDL) used to model electronic systems. Verilog HDL, not to be confused with VHDL (a competing language), is most commonly used in the design, verification, and implementation of digital logic chips at the register transfer level (RTL) of abstraction. It is also used in the verification of analog and mixed-signal circuits. Platform: |
Size: 28672 |
Author:nataraja |
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Description: Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard.-Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard.
Platform: |
Size: 1723392 |
Author:bom |
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Description: 2-to-4 Decoder with Testbench and Configuration
This set of design units illustrates several features of the VHDL language including:
Using generics to pass time delay values to design entities.
Design hierarchy using instantiated components.
Test benches for design verification.
Configuration declaration for binding components to design entities and setting delay values.-2-to-4 Decoder with Testbench and Configuration
This set of design units illustrates several features of the VHDL language including:
Using generics to pass time delay values to design entities.
Design hierarchy using instantiated components.
Test benches for design verification.
Configuration declaration for binding components to design entities and setting delay values. Platform: |
Size: 1024 |
Author:fangshan |
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Description: Like so many electronic test and measurement tools, a logic analyzer
is a solution to a particular class of problems. It is a versatile tool
that can help you with digital hardware debug, design verification
and embedded software debug. The logic analyzer is an indispensa- Platform: |
Size: 970752 |
Author:Thennavan |
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Description: 随机搜索大素数，随机生成公钥和私钥；
要求使用素性检测算法及高效率求逆和模幂运算 用私钥对任意长度的明文签名 用公钥对签名验证；-Random search large prime Numbers, random public key and a private key
Requires the use of element detection algorithm and efficient inverse power operation and mould With the private key for any plaintext signature length With the public key signature verification
Platform: |
Size: 6144 |
Author:胡佳敏 |
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Description: 各种kalman滤波器的设计，验证可用，计算多重分形非趋势波动分析，滤波求和方式实现宽带波束形成，GPS和INS组合导航程序，解耦，恢复原信号，与理论分析结果相比，包含CV、CA、Single、当前、恒转弯速率、转弯模型。- Various kalman filter design, Verification is available, Calculate the multifractal trend fluctuation analysis, Filtering summation way broadband beamforming, GPS and INS navigation program, Decoupling, restore the original signal, Compared with the results of theoretical analysis, It contains CV, CA, Single, current, constant turn rate, turning model. Platform: |
Size: 7168 |
Author:zvxnkwamr |
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Description: 介绍怎样去设计一种专用DSP
1. DSP fundamental,processor architectures, real-time system and design of embedded systems
2. Numberical representation and precision control of fixed-point number
3. ASIP and DSP architectures for different requirements and applications.
4. Intro to design methodologies for ASIP and DSP firmware
5. a DSP processor with an intuitive assembly instruction set
6. Profiling for ASIP IS design
7. IS design technique
8. Intro to toolchain
9. Benchmarking of assembly IS
10. Microarchitecture design
11. RF design
12. ALU
13. MAC
14. Control path
15. Design and implementation of memory subsys and address generators
16. DSP peripherals
17. funcational acceleration and DSP accelerators
18. Firmware design
19. Integration and verification of ASIP
20. parallel ASIP for streaming signal processing(embedded dsp processor design) Platform: |
Size: 17182720 |
Author:nickwang1982 |
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Search - design verification with