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[VHDL-FPGA-Verilog] Time

Description: ALTERA上DE2平台，利用内部50M Hz时钟，在数码管模拟显示时间(时分秒)。-ALTERA on DE2 platform, using internal 50M Hz clock, in the digital control simulation show time (hours minutes and seconds).
Platform: | Size: 609280 | Author: 徐朝凯 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 这是一个数字时钟的数字逻辑电路，整个工程打包上传，时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。-This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clock. The use of circuit implementation. The quatarsII inside the simulation, and downloaded to the DE2 board to run-off.
Platform: | Size: 1041408 | Author: ryan | Hits:

[VHDL-FPGA-Verilog] DigitalWatch

Description: Digital watch write in Verilog HDL language simulate the real clock in Atera DE2 development board
Platform: | Size: 15360 | Author: minh | Hits:

[VHDL-FPGA-Verilog] Digital-clock

Description: 数字钟工程，用QuartuesII软件开发的，在DE2-70上运行成功，可以直接使用，计时准确，文件代码简单，适合初学者借鉴。-Digital clock project, using QuartuesII software development, running on the DE2-70 success, can be used directly, accurate timing, file the code is simple, suitable for beginners learn.
Platform: | Size: 1019904 | Author: ricky | Hits:

[VHDL-FPGA-Verilog] clock-a-stopwatch

Description: 基于DE2-70平台，可实现功能： 1、在LCD上显示时间 2、在数码管上显示跑表-DE2-70-based platform, enabling functions: 1、display time on the LCD 2、display stopwatch the digital tube
Platform: | Size: 2048 | Author: Robert | Hits:

[VHDL-FPGA-Verilog] szsz

Description: 在DE2实验箱上实现数字时钟功能 包括了秒、分、时的基本显示功能-Implemented on the DE2 kit features include a digital clock seconds, minutes, when the basic display
Platform: | Size: 4096 | Author: cd | Hits:

[Books] DDE2E

Description: 使用 DE2板制作的多功能数字钟，含含有选择功能，秒表，电子表，闹钟，用7 -Produced using the DE2 board multi-function digital clock with contains a selection function, stopwatch, electronic watches, alarm clock, with 7
Platform: | Size: 3694592 | Author: guowai | Hits:

[OS program] shuzishizhong

Description: 用DE2做的数字钟，可以定时，调时间。用模块来搭建的数字钟，有详细的源代码。用DE2板可以直接实验。-DE2 to do with a digital clock, may from time to time, transfer time. With the modules to build digital clock, a detailed source code. Using DE2 board can be directly experiment.
Platform: | Size: 382976 | Author: YE | Hits:

[VHDL-FPGA-Verilog] m60

Description: 数字钟(for DE2 开发板) 1.‘时’、‘分’、‘秒’的十进制数字显示（小时从00～23）计时器。 2. 手动校时、校分、校秒的功能。 3．定时与闹钟功能，能在设定的时间发出闹铃声。 4．进行整点报时。从59分50秒起，每隔2秒钟发出一次低音“嘟”的信号，连续5次，最后一次发出高音“嘀”的信号，此信号结束即达到整点。 5、一个秒表，最低位1 秒、60秒，手动停止，手动重置。 6、一个倒计时，显示小时、分钟、秒，可设置时间。 -Decimal digital display (hour digital clock (for DE2 development board). ' ' , ' Minutes' , ' seconds' timer from 00 to 23). 2 when manually school, the school points School sec functionality. 3. Timer and alarm clock function, the alarm sounds at the set time. 4. The whole point of time. Starting at 59 minutes and 50 seconds, every 2 seconds issued time bass " beep" signal, five times in a row, the last issued a the treble " tick" signal, this signal the end to reach the whole point. 5, a stopwatch, the lowest 1 seconds, 60 seconds, manually stop manually reset. 6, a countdown display hours, minutes, seconds, set the time.
Platform: | Size: 908288 | Author: dai | Hits:

[VHDL-FPGA-Verilog] lab14

Description: DE2平台上实现的数字钟，包含时、分、秒的24小时制时间系统，有校时，准点报时，整点广播等功能。-DE2 platform digital clock, contains, minutes, seconds, 24-hour time system, school, prospective point of time, the whole point of broadcasting.
Platform: | Size: 1137664 | Author: DYQ | Hits:

[Other] clock

Description: 数字时钟led显示，de2开发板，HEX显示分秒-digital clock
Platform: | Size: 2048 | Author: 强书连 | Hits:

[VHDL-FPGA-Verilog] TIGERO

Description: VHDL语言设计老虎机的方案： 1、对DE2内部时钟实现分频，产生50hz的计数频率CLK； 2、用CLK作为计数时钟，分别实现三个计数器0~11,0~13,0~17，并将其计数结果中的个位数分别用三个七段数码管显示HEX1、HEX2、HEX3； 3、用CLK对DE2上的key1按键实现“定时方式去毛刺”输出K_Press信号，参见教材262； 4、利用K_Press信号的上升沿信号，实现Enable信号的翻转；Enable作为三个计数器的使能端，决定计数器的停止或者开始运行； 5、停止计数时，比较三个计数器的输出数字的相同个数N，并用七段数码管HEX4输出。N的结果分别为0、2、3；其中“0”表示三个数字中没有任何两个数字相同 -VHDL language program designed slot machine: 1, DE2 internal clock divider to generate 50hz frequency count of CLK 2, with the CLK as the count clock, respectively, to achieve three counters 0 ~ 11,0 ~ 13,0 ~ 17, and to count the results were used in the three-digit seven-segment LED display HEX1, HEX2, HEX3 3, with the CLK button for key1 DE2 on the realization of " regular way deburring" K_Press output signal, see textbooks 262 4 , the rising edge of the signal using the signal K_Press, flipping the Enable signal Enable counter as an enable terminal of three decision to stop or start operation of the counter 5, the counting is stopped, comparing the same number of three-digit counter output N, and pipe HEX4 segment digital output. Results N 0,2,3 respectively where " 0" indicates that no two of the three figures the same number
Platform: | Size: 2951168 | Author: 武生 | Hits:

[VHDL-FPGA-Verilog] clock2

Description: 基于Verilog HDL及DE2开发板的数字钟设计，使用Verilog HDL实现-Based on Verilog HDL and DE2 development board of the digital clock design, use Verilog HDL to implement
Platform: | Size: 581632 | Author: zhouyu | Hits:

[VHDL-FPGA-Verilog] DE2_LED_sm

Description: 驱动DE2—70开发板上数码管，并设计了一个时钟计数器，时钟计数时，分，秒。-DE2 70 development board driver digital tube, and designed a clock counter, clock count, minutes, seconds.
Platform: | Size: 861184 | Author: 李桐 | Hits:

[Other] digital_clk

Description: VHDL Code for a digital bit clock counter and 7 segment display clock on a altera DE2 board with a cyclone II FPGA
Platform: | Size: 950272 | Author: Casey | Hits:

[VHDL-FPGA-Verilog] shuzishizhong

Description: 基于DE2-115开发板设计的一个数字钟，能进行正常的小时、分、秒计时功能，并分别由开发板上面的数码管显示秒（60s）、分（60min）、小时（24hours）的时间。并具有手动调整时间的功能-DE2-115 board design based on a digital clock, and enables the normal hours, minutes, seconds chronograph function, and were above the development board digital display seconds (60s), points (60min), hours (24hours) time . And has a function to manually adjust the time
Platform: | Size: 3936256 | Author: luo | Hits:

[VHDL-FPGA-Verilog] 电子时钟

Description: 基于DE2-115的数字时钟 1.液晶显示，数码管显示 2.整点报时 3.闹钟 4.设置时间 5.设置闹钟(Digital clock based on DE2-115 1. LCD display, digital tube display 2. whole point 3. alarm clock 4. setting time 5. set the alarm clock)
Platform: | Size: 4921344 | Author: AZ1111 | Hits:

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