Description: 用Verilog DHL语言编写的一个数字钟程序,除了基本计数,还具有校时,闹钟功能-Verilog language used in the preparation of a digital clock procedures, in addition to the basic count, but also with school, an alarm clock Platform: |
Size: 1892 |
Author:谢树扬 |
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Description: 用Verilog DHL语言编写的一个数字钟程序,除了基本计数,还具有校时,闹钟功能-Verilog language used in the preparation of a digital clock procedures, in addition to the basic count, but also with school, an alarm clock Platform: |
Size: 2048 |
Author:谢树扬 |
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Description: 用Altera公司的QuartusII编写的电子钟程序，可以下载至开发板，实现一个智能数字钟功能，计时，校时，闹钟，跑表等功能，也可用于学习verilog HDL语言与数字逻辑-Using Altera s QuartusII procedures for the preparation of electronic bell, you can download to a development board, the realization of an intelligent digital clock function, time, school time, alarm clock, stopwatch functions can also be used to study verilog HDL language and digital logic Platform: |
Size: 2094080 |
Author:张欢 |
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Description: 此为多功能数字电子钟的vhdl代码，有闹钟、时间可调、计时等功能-This is a multi-function digital electronic clock VHDL code, has an alarm clock, time adjustable, timing and other functions Platform: |
Size: 4096 |
Author:naturexu |
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Description: 设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。
实验平台：
1. 一台PC机；
2. MAX+PLUSII10.1。
Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hours, minutes and seconds for manual adjustment to calibrate the time, whenever there is the whole point, resulting in timekeeping timekeeping tone. Experimental platform: 1. A PC machine 2. MAX+ PLUSII10.1. Verilog HDL language, as well as a complete experimental report Platform: |
Size: 425984 |
Author:盼盼 |
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Description: verilog语言实现的数字钟，各种定时闹钟功能类似真实的表~利用EDA实验平台实现-Verilog language implementation of the digital clock, alarm clock features a variety of regular table similar to the real experimental platform ~ using EDA implementation ~ ~ Platform: |
Size: 3072 |
Author:曹兵 |
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Description: 采用Verilog HDL语言编写的多功能数字钟，包括四个功能：时间显示与设置、秒表、闹钟、日期显示与设置.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings. Platform: |
Size: 3100672 |
Author:陈涵 |
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Description: 多功能数字钟Verilog HDL的源码，能够整点报时，报整点数，设定任意时刻闹钟，低音高音两种频率。-Multi-function digital clock Verilog HDL source code, set the alarm clock at any time, bass treble two frequencies. It s for FPGA. Platform: |
Size: 984064 |
Author:Stone Lei |
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Description: 用 Verilog HDL 设计一个多功能数字钟，包含以下主要功能：
1） 计时，时间以 24 小时制显示；
2） 校时；
3） 闹钟：设定闹钟时间，可利用 LED 闪烁作为闹钟提示；
4） 跑表：启动、停止；
5） 其他。-Using Verilog HDL design a multi-functional digital clock contains the following main functions: 1) time, the time is displayed in 24-hour clock 2) school 3) Alarm Clock: Set the alarm time, you can use the LED flashes as an alarm 4) Stopwatch: start, stop 5) Other. Platform: |
Size: 1234944 |
Author:毛洋 |
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Description: 利用vhdl和verilog两种方式可以实现的fpga芯片的数字钟，其中包含多个可设计改动的个性化模块。源代码利用quartusii平台写作，可移植性很强。-Using vhdl and verilog fpga can be achieved in two ways-chip digital clock, which includes several design changes personality module. Source code using the platform quartusii writing, portability is very strong. Platform: |
Size: 320512 |
Author:程煜河 |
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Description: verilog的数字钟代码，在XILINX上运行，可以手动设置时钟、闹钟，可报警-digital clock verilog code running on XILINX, you can manually set the clock, Alarm Clock, alarm Platform: |
Size: 11264 |
Author:严毅民 |
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Description: 采用可综合的Verilog代码编写一个带闹钟功能的数字钟。使其具有以下功能：
1)计时功能：包括小时、分钟、秒钟。
2)校时功能：对小时、分钟和秒钟进行手动校时。
3)定时和闹钟功能：能在手工设定的时间产生闹铃音。
-Using synthesizable Verilog coding a digital clock with alarm. It has the following features:
1) timing functions include: hours, minutes, seconds.
2) When the school functions: hours, minutes and seconds to the manual correction.
3) timing and alarm functions: to produce an alarm sound at the set time manually. Platform: |
Size: 2048 |
Author:shikai |
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Description: 原创数字钟verilog程序，能实现数字钟基本功能，如：计数，跑表，定时，闹钟。用于ISE软件。-Original digital clock verilog procedures, to achieve the basic functions of digital clock, such as: counting, stopwatch, timer, alarm clock. Platform: |
Size: 227328 |
Author:李悦 |
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Description: 采用Verilog HDL语言编写的多功能数字钟，包括四个功能：时间显示与设置、秒表、闹钟、日期显示与设置-.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings Platform: |
Size: 1024 |
Author:hup123456 |
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Description: 闹钟
工程说明
本工程包括矩阵键盘和数码管显示模块，共同实现一个带有闹钟功能、可设置时间的数字时钟。
案例补充说明
我们通过建立四个清晰直观的模块（数码管显示模块，矩阵键盘扫描模块，时钟计数模块，闹钟设定模块），以及建立完善的信号列表和运用verilog语言编写简洁流畅的代码，实现电子闹钟时、分、秒计时以及设置、修改、重置等功能。(alarm clock
Engineering description
This project includes matrix keyboard and digital display module, together with a digital clock with alarm clock function and set time.
Case Supplement
We build four clear and intuitive module (digital display module, matrix keyboard scanning module, clock counting module, alarm clock module), and establish and perfect the code signal list using Verilog language is concise and fluent, electronic clock, minutes and seconds, setting, modify, reset and other functions.) Platform: |
Size: 174080 |
Author:明德扬科教
|
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Search - digital clock verilog alarm