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[VHDL-FPGA-Verilog] vhdl_clock

Description: VHDL实现数字时钟，利用数码管和CPLD 设计的计数器实现一个数字时钟，可以显示小时，分钟，秒。程序主要要靠考虑十进制和六十进制计数器的编写。 以上实验的程序都在源代码中有详细的注释-VHDL digital clock, the use of digital control and CPLD design to achieve a number of counter clock, show hours, minutes and seconds. The procedure depends on the metric system and consider six decimal counter preparation. The experimental procedure in the source code for a detailed Notes
Platform: | Size: 324608 | Author: 赵海东 | Hits:

[VHDL-FPGA-Verilog] vhdl--timer

Description: 关于基于fpga的，数字化时钟vhdl实现源程序，推荐大家下载仿真实现。-On the FPGA-based, digital clock source VHDL realize recommend everyone to download simulation.
Platform: | Size: 6144 | Author: sxd | Hits:

[Other systems] clock_VHDL

Description: VHDL设计的数字时钟，有闹钟、整点报时等功能-VHDL design of the digital clock has an alarm clock, the whole point timekeeping functions
Platform: | Size: 510976 | Author: 王毅诚 | Hits:

[Embeded-SCM Develop] VHDL

Description: VHDL数字钟 数字电子钟 此数字电子钟具有的功能包括： 1. 计时，时、分、秒显示； 2. 十二小时与二十四小时之间的转换； 3. 上下午显示； 4. 对时、分、秒的校时功能；-VHDL digital clock digital clock digital electronic clock with this function include: 1. Time, hours, minutes and seconds display 2. 12 hours and 24 hours between the conversion 3. On the afternoon show 4. hours, minutes and seconds of the school function
Platform: | Size: 3072 | Author: HJGJGHK | Hits:

[Software Engineering] clock

Description: 基于vhdl的数字钟 有闹钟,秒表,时钟,日期等功能 秒表可以开始,暂停,清零, 时钟可以设置时间, 还可以设置日期-VHDL based on the digital clock has an alarm clock, stopwatch, clock, date, stopwatch functions can start, pause, cleared, the clock can be set-up times, you can set the date
Platform: | Size: 3072 | Author: 张廷 | Hits:

[Other] C2

Description: 功能更加完善的基于vhdl的数字时钟设计 有秒表，时钟，时期，闹钟的功能和整点报时，时间调整，日期调整，闹钟的设定 、、、、、、、 秒表有开始，暂停，清零等功能，且只有在暂停的情况下才能清零。-Function more complete VHDL-based design of the digital clock stopwatch, clock, time, alarm clock function and the whole point timekeeping, time adjustment, date, alarm clock settings ,,,,,,, stopwatch has started, pause, Clear and other functions, and only in the case of the suspension can be cleared.
Platform: | Size: 817152 | Author: 张廷 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 这是一个实现时分秒的时钟功能的源码，采用vhdl语言编写，已写好led驱动，可直接在数码管上显示-Realize this is an accurate clock function when the source code, the use of VHDL language has been written led drive directly in the digital tube display
Platform: | Size: 246784 | Author: xiaoshuai | Hits:

[source in ebook] VHDL_clock

Description: 数字钟 实现时、分、秒的显示和定时闹铃、整点报时等功能。-Realize digital clock hour, minute, second display and timing alarm, the whole point timekeeping functions.
Platform: | Size: 9216 | Author: 吴称光 | Hits:

[VHDL-FPGA-Verilog] electroclock

Description: VHDL的数字钟，内含各个模块的源程序，可直接运行-VHDL digital clock, each module contains the source code can be run directly
Platform: | Size: 82944 | Author: 玉峰 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字钟的VHDL源程序，可实现整点报时、闹钟的功能，还有常有星期的显示，已调试过-Digital Clock in VHDL source code, enabling the whole point timekeeping, alarm clock function, there are often weeks of shows that have been debug
Platform: | Size: 1339392 | Author: 玉峰 | Hits:

[VHDL-FPGA-Verilog] CLOCK

Description: 可以调整时间和设置闹钟的数字钟(VHDL)-Can adjust the time and set the digital clock alarm clock (VHDL)
Platform: | Size: 906240 | Author: iyoung | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字钟的程序，功能说明如下所示： 1.完成秒／分／时的依次显示并正确计数； 2.秒／分／时各段个位满10正确进位，秒／分能做到满60向前进位； 3.定时闹钟：实现整点报时，通过语音设备来实现具体的报时； 4.时间设置，也就是手动调时功能：当认为时钟不准确时，可以分别对分／时钟进行调整 5.可以选择使用12进制计时或者24进制计时。 使用QuartusII6.0编译仿真通过，语言使用的是VHDL，可以方便的移植到其他的平台上面。 -Digital clock procedures, functional description is as follows: 1. Completed sec/min/h and the sequence shows the correct count 2. Sec/min/h in the paragraphs of the correct 10-bit full binary, seconds/minutes to achieve the age of 60 to the forward position 3. regular alarm clock: realize the whole point of time, through the voice equipment to realize specific time 4. time settings, which is manually adjusted when the function: When the clock does not consider accurate, they can respectively sub/clock adjust 5. can choose to use 12 or 24 hexadecimal hexadecimal time time. QuartusII6.0 simulation through the use of compiler, language used is VHDL, can be easily ported to other platforms above.
Platform: | Size: 232448 | Author: 余宾客 | Hits:

[VHDL-FPGA-Verilog] shuzizhong

Description: 数字钟代码，用VHDL语言设计一个数字钟系统，该系统具有显示时、分、秒的功能，具有较时功能，具有整点报时功能。-Digital Clock code using VHDL language to design a digital clock system, which has a display hours, minutes and seconds functions, when a more functional, with the whole point timekeeping function.
Platform: | Size: 1024 | Author: SDFG | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字秒表的设计，reset为归零设置，start为重新计时设置-Design of digital stopwatch, reset to zero settings, start time set for the re-
Platform: | Size: 309248 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] multifunction_digital_clock_based_on_fpga

Description: 基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码，其功能主要有：时间设置，时间显示，跑表，分频，日期设置，日期显示等-FPGA-based multi-functional Digital Clock Design and Implementation of typhoons and rainstorms are detailed Verilog HDL source code, its functions include: time settings, time display, stopwatch, frequency, date setting, date display
Platform: | Size: 3293184 | Author: | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字钟设计，有分秒显示，上下午显示，可下载到FPGA板子上进行数字显示哦-Digital clock design, there are minutes and seconds display, on the afternoon of shows can be downloaded to the FPGA on the board figures show Oh
Platform: | Size: 3072 | Author: 幸福 | Hits:

[Embeded-SCM Develop] vhdl-digital-clock-design

Description: 设计一个具有特定功能的数字电子钟。准确计时，以数字形式显示h、min、s 的时间。小时的计时要求为二十四进位，分和秒的计时要求为六十进位。 该电子钟上电或按键复位后能自动显示系统提示00-00-00，进入时钟准备状态；第一次按电子钟功能键，电子钟从0时0分0秒开始运行，进入时钟运行状态；再次按电子钟功能键，则电子钟进入时钟调整状态，此时可利用各调整键调整时间，调整结束后可按功能键再次进入时钟运行状态。 -Designed with a specific function of a digital electronic clock. Accurate timing to the digital form h, min, s time. Hours of time requested for the 24 binary, minutes, and seconds of time requested for the 60 binary. The electronic bell power or reset button can automatically display 00-00-00 prompted, enter the clock readiness the first time by e-bell function keys, the electronic bell from 00:00:00 to start running, enter the clock running again by e-bell function keys, the electronic bell to enter the clock adjustment status, at this time can use the adjustment button to adjust the time to adjust after the end of function keys can be re-entering the clock running.
Platform: | Size: 6144 | Author: andy | Hits:

[assembly language] clock

Description: 数字钟是采用数字电路实现“时”、“分”、“秒”数字显示的计时装置。由于数字集成电路的发展和石英晶体震荡器的使用，使得数字钟的精度、稳定度远远超过了机械钟表，已成为人们日常生活中必不可少的必需品。-Digital Clock is a digital circuit implementation, " when" , " sub" , " second" The figures show that the timing device. Digital integrated circuits because of the development and use of quartz crystal oscillator, making the accuracy of the number of minutes, far exceeding the stability of mechanical clocks and watches, has become essential daily necessities.
Platform: | Size: 338944 | Author: 庄青青 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 采用Verilog HDL语言编写的多功能数字钟，包括四个功能：时间显示与设置、秒表、闹钟、日期显示与设置.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings.
Platform: | Size: 3100672 | Author: 陈涵 | Hits:

[VHDL-FPGA-Verilog] digital-clock-design

Description: VHDL语言编写的数字时钟设计程序，含源代码和波形仿真，还有顶层电路设计。-The VHDL language of the digital clock design procedures, including source code and the waveform simulation, but also the circuit design.
Platform: | Size: 13312 | Author: h | Hits:
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