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[Communication] gfuzzy

Description: 基于模糊逻辑控制的数字锁相环，用于通信系统中的载波恢复。Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system.
Platform: | Size: 34007 | Author: gogomx | Hits:

[Other resource] 数字锁相环

Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
Platform: | Size: 125197 | Author: 于洪彪 | Hits:

[VHDL-FPGA-Verilog] 数字锁相环

Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
Platform: | Size: 124928 | Author: 于洪彪 | Hits:

[Software Engineering] ACarrierTrackingAlgorithmBasedOnFPLL

Description: 介绍了一种基于锁频锁相环(FPLL)的载波跟踪算法。频率跟踪模块可以适应较大动态范围的频率变化，基于软件的数控振荡器(NCO)模块可以达到极高的频率跟踪精度。由于有锁频环的频率牵引，锁相环路滤波器可以设计得很窄，具有很好的抑噪性能，满足精确跟踪载波相位的要求。因此，该基于FPLL的载波跟踪算法可以适应信号存在较大的动态范围和噪声干扰的应用环境；同时，其鉴频鉴相算法表达式简单，易于用可编程数字器件实现。-Introduce an approach based on frequency-locking phase-locked loop (FPLL) carrier tracking algorithm. Frequency tracking module can adapt to a larger dynamic range of the frequency change, software-based numerical control oscillator (NCO) module can achieve the very high frequency tracking accuracy. Because of the frequency lock loop traction PLL filter can be designed very narrow, with very good noise suppression performance, to meet the precise requirements of carrier phase tracking. Therefore, the FPLL carrier-based tracking algorithm can be adapted to signal the existence of a larger dynamic range and noise of the application environment at the same time, the PFD algorithm expression is simple, easy to use programmable digital devices.
Platform: | Size: 162816 | Author: 何宁 | Hits:

[Communication] gfuzzy

Description: 基于模糊逻辑控制的数字锁相环，用于通信系统中的载波恢复。Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system.-Based on fuzzy logic control of digital phase-locked loop for the communication system in carrier recovery. Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system.
Platform: | Size: 33792 | Author: gogomx | Hits:

[VHDL-FPGA-Verilog] DPLL(VHDL)

Description: 使用VHDL语言进行的数字锁相环的设计，里面有相关的文件，可以使用MUX+PLUS打开-The use of VHDL language of digital phase-locked loop design, there are relevant documents, you can use MUX+ PLUS Open
Platform: | Size: 13312 | Author: 国家 | Hits:

[VHDL-FPGA-Verilog] PLL

Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上； 顶层文件是PLL.GDF-Digital phase-locked loop PLL is the design source code, which, Fi is the input frequency (receive data), Fo (Q5) is a local output frequency. The purpose is to extract data from the input clock signal (Q5), their frequency and data rate in line clock rising edge of lock-in data on rising and falling edge PLL.GDF top-level document
Platform: | Size: 126976 | Author: 许伟 | Hits:

[VHDL-FPGA-Verilog] DPLL

Description: 全数字锁相环的verilog设计，已通过仿真验证能迅速锁定相位-Digital phase loop lock design with verilog
Platform: | Size: 1024 | Author: yangyanwen | Hits:

[matlab] DPLL

Description: 模数转换的数字锁相环，代码中有详细的说明-digital phase lock loop
Platform: | Size: 2048 | Author: 张 | Hits:

[VHDL-FPGA-Verilog] PLL

Description: 在同步控制上，应用了“优先与抢占”的方式产生同步信号，纯硬件实现，简单可靠；使用了成熟的数字锁相环来跟踪同步信号。-A strategy of synchronization control, which combines competition coequality and priority, is mentioned in the paper and uses digital phase-lock loop to track synchronization signal
Platform: | Size: 5120 | Author: wang | Hits:

[VHDL-FPGA-Verilog] weitb

Description: 在数字通信中，通常直接从接收到的数字信号中提取位同步信号，这种直接法按其提取同步信号的方式，大致可分为滤波法和锁相法。锁相法是指利用锁相环来提取位同步信号的方法，本设计方案就是基于锁相环的位同步提取方法，能够比较快速地提取位同步时钟，并且设计简单，方便修改参数。采用Quartus II设计软件对系统进行了仿真试验，并用Altera的Cyclone II系列FPGA芯片Ep2c5予以实现。-In digital communication, usually from receiving directly in digital signal extracted a synchronized signal, the direct method according to the extraction synchronized signal way, can be roughly divided into filtering method and phase lock method. Phase lock method is using of phase locked loop to extract a synchronized signal method, the design scheme is based on phase locked loop of a synchronous extraction method and can be quickly extract a synchronous clock, and design simple, convenient modification parameter. The Quartus II design software of the system, and the simulation test Altera Cyclone II FPGA chip to achieve Ep2c5 series.
Platform: | Size: 595968 | Author: dandan | Hits:

[SCM] ANOlog_TMS320F28335

Description: 本装置采用单相桥式DC-AC逆变电路结构，以TI公司的浮点数字信号控制器TMS320F28335 DSP为控制电路核心，采用规则采样法和DSP片内ePWM模块功能实现SPWM波。最大功率点跟踪（MPPT）采用了恒压跟踪法（CVT法）来实现，并用软件锁相环进行系统的同频、同相控制，控制灵活简单。采用DSP片内12位A/D对各模拟信号进行采集检测，简化了系统设计和成本。本装置具有良好的数字显示功能，采用CPLD自行设计驱动的4.3’’彩色液晶TFT LCD非常直观地完成了输出信号波形、频谱特性的在线实时显示，以及输入电压、电流、功率，输出电压、电流、功率，效率，频率，相位差，失真度参数的正确显示。本装置具有开机自检、输入电压欠压及输出过流保护，在过流、欠压故障排除后能自动恢复。-This device single-phase bridge type DC-AC inverter circuit structure, TI company of floating in digital signal controller TMS320F28335 DSP as the control circuit, the core rules sampling method and DSP piece ePWM module function realization within SPWM wave. The maximum power point tracking (MPPT) used the constant pressure tracking method (CVT method) to realize the software, and phase lock loop to carry on the system the same frequency, phase control, control with flexible simple. By using DSP piece of 12 within the A/D of each simulation signal acquisition detection, simplified system design and cost. This device has a good digital display function, use CPLD to design the driver 4.3 " TFT LCD color LCD very intuitive to finish the output signal waveform and spectrum characteristics of online real-time display, and the input voltage, current, power, the output voltage, current, power, efficiency, frequency, phase difference, the distortion degree of parameters display properly. Thi
Platform: | Size: 5020672 | Author: 徐徐 | Hits:

[VHDL-FPGA-Verilog] eda

Description: EDA 正弦信号发生器：正弦信号发生器的结构有四部分组成，如图1所示。20MHZ经锁相环PLL20输出一路倍频的32MHZ片内时钟,16位计数器或分频器CNT6，6位计数器或地址发生器CN6，正弦波数据存储器data_rom。另外还需D/A0832（图中未画出）将数字信号转化为模拟信号。此设计中利用锁相环PLL20输入频率为20MHZ的时钟，输出一路分频的频率为32MHZ的片内时钟，与直接来自外部的时钟相比，这种片内时钟可以减少时钟延时和时钟变形，以减少片外干扰 还可以改善时钟的建立时间和保持时间，是系统稳定工作的保证。CNT6用来将32MHZ进行8分频得到4096HZ的频率提供给CN6与data_rom时钟信号。由CLK端输入20MHZ的时钟信号，在DOUT端就可输出稳定的正弦信号。-Sine signal generator has the structure of four parts, as shown in figure 1 below. The 20 MHZ phase lock loop PLL20 output all the way of frequency doubled within 32 MHZ slice clock, 16 counter or prescaler CNT6, six counter or address generator CN6, sine data storage data_rom. In addition to D/A0832 (shown in not draw) will digital signal into analog signals. This design using the phase lock loop PLL20 input frequency for 20 MHZ clock, the output of the frequency of all points frequency of 32 pieces (MHZ clock, and comes directly from the external clock, compared to this piece of clock can reduce the clock in delay and clock deformation, to reduce the interference of Can also improve the establishment of the clock time and keep time, is the system stability of assurance. CNT6 used to will and to 8 MHZ get 4096 HZ dividing the frequency to provide CN6 and data_rom clock signal. The input by CLK 20 MHZ clock signal, in DOUT end can output stable sine signals.
Platform: | Size: 33792 | Author: 王丽丽 | Hits:

[Modem program] Design-of-All-Digital-FM-Receiver-Circuit

Description: all digital phase lock loop
Platform: | Size: 658432 | Author: chenxiaomao | Hits:

[VHDL-FPGA-Verilog] dpll

Description: 用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证-verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider
Platform: | Size: 6144 | Author: chi zhang | Hits:

[Other] digital-phase-locked-loop-

Description: 基于FPGA的数字锁相环的研究与实现,锁相速度快。-The study of the digital phase-locked loop based on FPGA and implementation, fast phase lock.
Platform: | Size: 1235968 | Author: 安慧林 | Hits:

[Other] 基于DSP的60kW_300kHz高频感应加热电源

Description: 介绍了一种基于DSP 的高频感应加热电源。现以MOSFET为开关器件，并通过逆变器并联扩容为60kW/300kHz。采用多重斩波技术，增大了斩波电路的容量，将基于DSP 的fuzzy-DPLL 复合数字锁相环技术应用在高频场合，使锁相有快速的动态性能和高精度的稳态性能，实现了对负载频率的可靠跟踪及对逆变状态的可靠控制，提高了逆变器 的工作效率和功率因数。(A high frequency induction heating power supply based on DSP. MOSFET is now used as a switch device, and the capacity of 60kW/300kHz is expanded in parallel through the inverter.Using multiple chopping technology, the capacity of chopper circuit is increased, and the fuzzy-DPLL composite digital phase locked loop technology based on DSP is applied to the high frequency situation, so that the lock is locked.It has fast dynamic performance and high precision steady state performance. It achieves reliable tracking of load frequency and reliable control of inverter state, and improves inverter.Working efficiency and power factor.)
Platform: | Size: 751616 | Author: destyni | Hits:

[SCM] ADF4355 数据手册

Description: ADF4355是微波宽带(54-6800MHz)可实现小数N分频或整数N分频锁相环(PLL)的频率合成器,高分辨率38位模数,低相位噪声电压控制振荡器(VCO),可编程1/2/4/8/16/32/64分频输出,模拟和数字电源为3.3 V,主要用在无线基础设施（W-CDMA,TD-SCDMA,WiMAX,GSM, PCS,DCS,DECT）,点到点/点到多点微波链路(ADF4355 microwave broadband (54-6800 MHZ) can realize the decimal frequency or integer N N points points frequency and phase lock loop (PLL) frequency synthesizer, 38 modulus, high resolution and low phase noise voltage controlled oscillator (VCO), programmable 1/2/4 8/16/32/64 frequency output, analog and digital power supply of 3.3 V, mainly used in wireless infrastructure (w-cdma, td-scdma, WiMAX, GSM, PCS, DCS, DECT), point-to-point/point to multipoint microwave links)
Platform: | Size: 764928 | Author: 悟与 | Hits:

[hardware design] dpll源程序

Description: 一种设计数字锁相环的思路，包含异或鉴相器、k模可逆计数器、脉冲加减计数器、N分频器等，实现相位的锁定。(A design of digital phase locked loop (PLL) consists of a phase discriminator, a K mode reversible counter, a pulse addition and subtraction counter, a N frequency divider and so on, to lock the phase.)
Platform: | Size: 1024 | Author: 和风5254 | Hits:

[DSP program] 基于DSP28335的单相PWM整流 双闭环PI控制

Description: 利用DSPF28335实现单相桥式PWM整流器的双闭环PI控制，用到AD7606和数字锁相(Double-closed-loop PI control of single-phase bridge PWM rectifier using DSPF28335, using AD7606 and digital phase lock)
Platform: | Size: 18432 | Author: 糊涂小兵 | Hits:
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