Search - digital_clock

[Embeded-SCM Develop] Digital_Clock

Description: 数字时钟:LCD+凌阳SPCEO61A,通过中断计时,LCD显示,界面简洁宜人-Digital Clock : LCD Sunplus SPCEO61A through interruption time, LCD display, Pleasant simple interface
Platform: | Size: 9537 | Author: 易成 | Hits:

[Other resource] digital_clock

Description: 用verlog语言编的一个很好的综合实验,特别适合于FPGA/CPLD的初学者-verlog language with a good addendum to the comprehensive experiment, particularly suitable for FPGA / CPLD beginners
Platform: | Size: 273296 | Author: leolili | Hits:

[Other resource] digital_clock

Description: 基于AT89S52的自动报时数字闹钟. 该数字钟具有整点报时和闹钟功能，时间显示为时.分.秒，以12小时制显示。可通过按键调整时间的小时位和分钟位，整点和闹钟均以闪烁方式报时。程序分为以下模块：数码管显示模块，控制显示模块，定时器T0中断处理模块，定时器T1中断处理模块，键盘扫描模块，键盘处理模块，延时模块和整点闪烁模块
Platform: | Size: 2869 | Author: 陈 | Hits:

[Other resource] Digital_Clock-7Seg

Description: Digital Clock Source using ATmega8515 and 7Segment
Platform: | Size: 23698 | Author: kang | Hits:

[Other resource] digital_clock

Description: 用veriolg写的数字钟实验，具有定点报时，闰年判断，年月日显示，下载平台为spantan3s400。有详细注解。适合verilog学习
Platform: | Size: 1186844 | Author: 屠宁杰 | Hits:

[Other resource] digital_clock

Description: 单片机源代码,数字实时钟,C源码,KEIL C开发环境.
Platform: | Size: 139956 | Author: williamguo | Hits:

[Embeded-SCM Develop] Digital_Clock

Description: 数字时钟:LCD+凌阳SPCEO61A,通过中断计时,LCD显示,界面简洁宜人-Digital Clock : LCD Sunplus SPCEO61A through interruption time, LCD display, Pleasant simple interface
Platform: | Size: 36864 | Author: 易成 | Hits:

[VHDL-FPGA-Verilog] digital_clock

Description: 用verlog语言编的一个很好的综合实验,特别适合于FPGA/CPLD的初学者-verlog language with a good addendum to the comprehensive experiment, particularly suitable for FPGA/CPLD beginners
Platform: | Size: 273408 | Author: leolili | Hits:

[SCM] digital_clock

Description: 基于AT89S52的自动报时数字闹钟. 该数字钟具有整点报时和闹钟功能，时间显示为时.分.秒，以12小时制显示。可通过按键调整时间的小时位和分钟位，整点和闹钟均以闪烁方式报时。程序分为以下模块：数码管显示模块，控制显示模块，定时器T0中断处理模块，定时器T1中断处理模块，键盘扫描模块，键盘处理模块，延时模块和整点闪烁模块-AT89S52 based on automatic timekeeping digital alarm clock. The whole point of digital clock with timer and alarm clock function, time display too. Sub. Seconds to 12-hour show. Buttons adjust the time by the hour and minute-bit-bit, the whole point and the alarm time are blinking manner. Procedures are divided into the following modules: digital tube display module, control module, processing module interrupt timer T0, T1 timer interrupt handling module, the keyboard scan module, the keyboard processing module, delay module and the whole point of flashing module
Platform: | Size: 3072 | Author: 陈 | Hits:

[SCM] Digital_Clock-7Seg

Description: Digital Clock Source using ATmega8515 and 7Segment
Platform: | Size: 23552 | Author: kang | Hits:

[VHDL-FPGA-Verilog] digital_clock

Description: 用veriolg写的数字钟实验，具有定点报时，闰年判断，年月日显示，下载平台为spantan3s400。有详细注解。适合verilog学习-Written by veriolg digital clock experiments with fixed time, to determine leap year, date display, download platform spantan3s400. Have a detailed annotation. Suitable for learning Verilog
Platform: | Size: 1186816 | Author: 屠宁杰 | Hits:

[SCM] digital_clock

Description: 单片机源代码,数字实时钟,C源码,KEIL C开发环境.-Single-chip source code, the number of real-time clock, C source, KEIL C development environment.
Platform: | Size: 139264 | Author: williamguo | Hits:

[Software Engineering] digital_clock

Description:
Platform: | Size: 2393088 | Author: guolh | Hits:

[SCM] digital_clock

Description: 基于C语言编程的keil单片机有关数学时钟的设计，比起汇编，C语言更具简洁性-Based on C language programming keil Singlechip clock on the mathematical design, compared to the compilation, C language is more concise and
Platform: | Size: 1024 | Author: 潘尚德 | Hits:

[Embeded-SCM Develop] Digital_Clock

Description: 使用汇编语言实现数字时钟设计，用7seg完成显示，并可以通过button对时钟进行调整。并包括系统仿真原理图，适合做设计者使用-The use of assembly language to achieve digital clock design, with the completion of 7seg show, and can adjust the button on the clock. And includes system simulation schematic diagram, suitable for designers to use
Platform: | Size: 149504 | Author: wl | Hits:

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[Embeded-SCM Develop] Digital_Clock

[Other resource] digital_clock

[Other resource] digital_clock

[Other resource] Digital_Clock-7Seg

[Other resource] digital_clock

[Other resource] digital_clock

[Embeded-SCM Develop] Digital_Clock

[VHDL-FPGA-Verilog] digital_clock

[SCM] digital_clock

[SCM] Digital_Clock-7Seg

[VHDL-FPGA-Verilog] digital_clock

[SCM] digital_clock

[Software Engineering] digital_clock

[SCM] digital_clock

[Embeded-SCM Develop] Digital_Clock

[SCM] c51.digital_clock

[Other] Digital_Clock

[VHDL-FPGA-Verilog] digital_clock

[2D Graphic] Digital_clock

[VHDL-FPGA-Verilog] digital_clock

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