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[Other] verilog_lcd

Description: 用Verilog HDL 语言写的在LCD液晶上显示文字的源程序-with Verilog HDL write on the LCD display text of the source
Platform: | Size: 423936 | Author: yhr | Hits:

[VHDL-FPGA-Verilog] LED47DISP

Description: 4-7segment led display Verilog code. Implemented at Stratix EP1S25 DSP development board.-4-7segment led display Verilog code. Impl emented at Stratix EP1S25 DSP development boar d.
Platform: | Size: 2048 | Author: iamz | Hits:

[VHDL-FPGA-Verilog] 9.2_LCD_PULSE

Description: 基于Verilog-HDL的硬件电路的实现 9.2 具有LCD显示单元的可编程单脉冲发生器 　　9.2.1 LCD显示单元的工作原理 　　9.2.2 显示逻辑设计的思路与流程 　　9.2.3 LCD显示单元的硬件实现 　　9.2.4 可编程单脉冲数据的BCD码化 　　9.2.5 task的使用方法 　　9.2.6 for循环语句的使用方法 　　9.2.7 二进制数转换BCD码的硬件实现 　　9.2.8 可编程单脉冲发生器与显示单元的接口 　　9.2.9 具有LCD显示单元的可编程单脉冲发生器的硬件实现 　　9.2.10 编译指令-"文件包含"处理的使用方法 -based on Verilog-HDL hardware Circuit of 9.2 LCD display module with the series Single-Pulse Generator 9.2.1 LCD display module Principle 9.2.2 shows the logic design Thinking and Process 9.2.3 LCD display module hardware 9.2.4 programmable single pulse data BCD of the task 9.2.5 9.2.6 for the use of the phrase cycle use 9.2.7 binary conversion of BCD programmable hardware 9.2.8 single pulse generator with a said unit 9.2.9 interface with the LCD display module programmable pulse generator hardware 9 .2.10 compiler directives- "document includes" the use of
Platform: | Size: 5120 | Author: 宁宁 | Hits:

[VHDL-FPGA-Verilog] dynamic_display

Description: 4 digital LED dynamic display的Verilog HDL源代码，它能动态的显示4位数，为FPGA 的DEBUG 提供便利，非常经典，简单易懂，并且经过了Modelsim/ISE/FPGA(XC3S250ETQ144)验证和实现，好的行为模型就应该大家分享。-4 digital LED dynamic display of the Verilog HDL source code, it can dynamically display 4-digit for the FPGA to facilitate the DEBUG, very classic, easy-to-read, and after Modelsim/ISE/FPGA (XC3S250ETQ144) authentication and realize, good The behavior model should be shared.
Platform: | Size: 257024 | Author: name | Hits:

[VHDL-FPGA-Verilog] DE2_SD_Card_Audio

Description: SD卡读取音频数据，由VGA显示。Verilog HDL语言编写，适用DE2实验箱-SD card reader audio data from the VGA display. Verilog HDL language, the application of the experimental box DE2
Platform: | Size: 3072 | Author: 白雪 | Hits:

[assembly language] EEPROMpresentation

Description: 利用拨码开关为可编程器件输入读写命令和相应的地址、数据，8051读入可编程器件设定的命令字并根据可编程器件的设置进行读写操作，读出来的数据通过P0输出给可编程器件，并由可编程器件控制七段数码管显示。(Verilog+单片机)-DIP switch for the use of programmable devices to read and write command input and the corresponding address, data, read into the programmable device 8051 set the word order and in accordance with programmable device settings for read and write operations, read out the data through P0 output to the programmable device, programmable device controlled by the Seven-Segment LED display. (Verilog+ Singlechip)
Platform: | Size: 3072 | Author: 辛颖 | Hits:

[VHDL-FPGA-Verilog] FPGA-LCD1602

Description: 基于FPGA的LCD1602显示，可根据实际内容修改显示内容-FPGA-based LCD1602 display can be modified according to the actual contents of display content
Platform: | Size: 489472 | Author: 冀少威 | Hits:

[VHDL-FPGA-Verilog] DE2_70_TV

Description: --- --- --- -Verilog--- --- ---- This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor. Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.--------------------Verilog---------------- This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor. Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.
Platform: | Size: 168960 | Author: Sami | Hits:

[SCM] LCD

Description: LCD显示的完整代码，采用Verilog编写-LCD display complete code, the use of Verilog to prepare
Platform: | Size: 405504 | Author: 陈成 | Hits:

[VHDL-FPGA-Verilog] dem4bit_hienthi

Description: the verilog source code for being an examble to counts 4-bit number and display in 7-segment.
Platform: | Size: 318464 | Author: connit1986 | Hits:

[VHDL-FPGA-Verilog] LCD_Top

Description: FPGA 的verilog LCD显示代码-FPGA code in verilog LCD display
Platform: | Size: 3072 | Author: xcxscf | Hits:

[VHDL-FPGA-Verilog] 1602LCD

Description: 1602lcd 显示程序，用Verilog语言编写，经测试程序运行没有问题！-1602lcd display program, with the Verilog language, tested program is running there is no problem!
Platform: | Size: 70656 | Author: 韩瑞 | Hits:

[VHDL-FPGA-Verilog] verilog-VGA

Description: 在FPGA内，实现简单的VGA显示功能。verilog源代码-In the FPGA, the realization of a simple VGA display. verilog source code
Platform: | Size: 2048 | Author: niuqs | Hits:

[VHDL-FPGA-Verilog] vga

Description: verilog file , FPGA controll vga display- verilog file , FPGA controll vga display
Platform: | Size: 203776 | Author: panchao | Hits:

[Other] verilog

Description: verilog code for a microwave controller with clock output, clock time setting input, power control input+output, cooking timer setup, door open light, cooking complete buzzer output. Four push buttons provide following active low input signals: 1) KEY0 …………func_n 2) KEY1………….ten_sec_setup_n 3) KEY2………….one_min_setup_n 4) KEY3………….ten_min_setup_n Two high/low switches provide following input signals: 1) SW0……………reset_n 2) SW1……………open_door Three output signals to LEDs provide following functionality 1) LEDG0…………to_buzzer 2) LEDG1…………cook_enable 3) LEDG2…………to_lamp There are also four seven-bit signals going to 7-segemnt display 1) HEX0…………..to_sseg0 2) HEX1…………..to_sseg1 3) HEX2…………..to_sseg2 4) HEX3…………..to_sseg3-verilog code for a microwave controller with clock output, clock time setting input, power control input+output, cooking timer setup, door open light, cooking complete buzzer output. Four push buttons provide following active low input signals: 1) KEY0 …………func_n 2) KEY1………….ten_sec_setup_n 3) KEY2………….one_min_setup_n 4) KEY3………….ten_min_setup_n Two high/low switches provide following input signals: 1) SW0……………reset_n 2) SW1……………open_door Three output signals to LEDs provide following functionality 1) LEDG0…………to_buzzer 2) LEDG1…………cook_enable 3) LEDG2…………to_lamp There are also four seven-bit signals going to 7-segemnt display 1) HEX0…………..to_sseg0 2) HEX1…………..to_sseg1 3) HEX2…………..to_sseg2 4) HEX3…………..to_sseg3
Platform: | Size: 17408 | Author: ddr | Hits:

[VHDL-FPGA-Verilog] seg

Description: 数码管显示（verilog） 自己写的 在数码管上显示01234567 动态显示-Digital LED display (verilog) himself wrote in the digital tube display 01234567 dynamic display
Platform: | Size: 1024 | Author: Along | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 主要包含了用verilog语言别写的实用于视频例如LCD等显示设备的音频与视频的控制系统，其中包括了延时代码的编写模块，希望对坐显示的有所帮助!-It contains the verilog language with written and practical at the videos of other LCD and other display devices such as audio and video control systems, including the delayed preparation of the code module, want to take display help!
Platform: | Size: 9216 | Author: 熊文 | Hits:

[VHDL-FPGA-Verilog] FPGA-verilog

Description: 用Verilog语言编写的一些简单的FPGA入门实验，用ALTERA DE2开发板和Quartus_II软件开发环境。包括：流水灯实验、数码管显示实验-With Verilog language preparation some simple introduction experiment, with FPGA ALTERA DE2 development board and Quartus_II software development environment. Include water lamp experiment, digital pipe display experimentation, etc
Platform: | Size: 10240 | Author: 星光依旧 | Hits:

[VHDL-FPGA-Verilog] verilog-vga

Description: Verilgo编写的VGA显示接口示例程序, 在显示器上显示矩形彩条, 包含Quartus II 8.1工程文件及VGA的相当资料(PDF及WORD文档)-Verilgo prepared VGA display interface sample program, the color of the rectangle on the display, including the Quartus II 8.1 project file and VGA considerable data (PDF and WORD document)
Platform: | Size: 1771520 | Author: Joseph | Hits:

[VHDL-FPGA-Verilog] DE1-Practice-VGA-display-

Description: 用altera的fpga设计的DE1开发板作为硬件平台实现VGA显示，verilog实现的，8种色彩，作为fpga驱动vga液晶的入门。DE1实践之VGA显示（8bit色彩）-Altera fpga design with the DE1 board as a hardware platform development VGA display, verilog implementation, 8 colors, as the introduction to fpga driver vga LCD--- DE1 Practice VGA display (8bit color)
Platform: | Size: 13312 | Author: wuwei | Hits:
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