Location:
Search - dma ip core
Search list
Description: DMA的控制器的IP核,和ATA控制器配合,可以实现DMA方式高速传输数据.-DMA controller IP core, and ATA controller tie, DMA can achieve high-speed transmission of data.
Platform: |
Size: 143596 |
Author: 李想 |
Hits:
Description: Wishbone dma ip core
Platform: |
Size: 7081 |
Author: liwen |
Hits:
Description: DMA的控制器的IP核,和ATA控制器配合,可以实现DMA方式高速传输数据.-DMA controller IP core, and ATA controller tie, DMA can achieve high-speed transmission of data.
Platform: |
Size: 143360 |
Author: 李想 |
Hits:
Description: Wishbone dma ip core
Platform: |
Size: 7168 |
Author: liwen |
Hits:
Description: DMA VHDL 设计IP核经常遇到大数据交换要用DMA，本IP核来自开源组织，免费开源版-DMA VHDL design IP core often encountered in large data exchange to use DMA, the IP core from the open-source organizations, free open source version
Platform: |
Size: 93184 |
Author: |
Hits:
Description: Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转，以便适应手持式设备在移动环境中图像的捕捉。可变的同步信号极性使得可以兼容各种摄像头外设。Camera Interface兼容AMBA规范， AHB SLAVE接口，用于读取软件配置数据和设置数据存放地址和1帧数据占用的空间。-The Camera IP Core is small and flexible video data coverter. It is connected to a typical video camera ICs with 8-bit digital video data, Horizontal synchronization and Vertical synchronization signals. The core is connected through FIFO to a WISHBONE bus on the other side. Both sides of the core can operate at fully asynchronous clock frequencies. The Camera IP Core convertes 4:2:2 YCbCr video data (sometimes called YUV, but not totally the same Y is the same, while Cb and Cr are U and V multiplied by a constant) to a 24-bit RGB. 24-bit or 16-bit RGB data, downsampled from 24-bit RGB, is then sent to the system (video) memory, however conversion can also be by-passed. Interrupt can be generated after frame-buffer in system (video) memory is filled up or after setable number of horizontal lines written to frame-buffer.
Platform: |
Size: 32768 |
Author: 孙喆 |
Hits:
Description: 基于wishbone总线的SD Card IP Core,有Verilog和VHDL两种语言版本,包含了FIFO和DMA两种实现方式,是开源的IP Core-Based on the wishbone bus SD Card IP Core, there are two language versions of Verilog and VHDL, including the FIFO and DMA implemented in two ways, is open source IP Core
Platform: |
Size: 2271232 |
Author: 张亚群 |
Hits:
Description: Altera公司可编程DMA控制器A8237的IP核host_dec模块-Altera, The Programmable DMA controller IP core host_dec module A8237
Platform: |
Size: 3072 |
Author: 张曼 |
Hits:
Description: SOPC系统编译的DMA的Verilog代码-DMA IP core in SOPC
Platform: |
Size: 5120 |
Author: zy |
Hits:
Description: 这是一个简单IP核的DMA桥，他有两个WISHBONE接口，该平台可实现在两个相同或不同接口之间DMA数据的搬运。-This is a simple DMA/Bridge IP core. It has two WISHBONE interface. It can perform DMA transfers between the two interfaces or on the same interfaces.
Platform: |
Size: 143360 |
Author: 云海 |
Hits:
Description: 本文档介绍了一种基于Xilinx Endpoint Block Plus PCIe IP Core，由板卡主动发起的DMA设计。该设计利用通用的LocalLink 接口，所以方便的兼容支持Xilinx PCIe 硬核的器件，例如Virtex 5，Virtex 6，Spartan 6，并且实际在ML555 和ML605 开发板上实际测试通过。此外，驱动将板卡的控制封装起来，提供用户层简单的读写接口，方便上层程序的开发。-This document describes an approach based on Xilinx Endpoint Block Plus PCIe IP Core, initiated by the board of DMA Design. The design utilizes a common LocalLink interface, easy to support Xilinx PCIe hardcore compatible devices, such as Virtex 5, Virtex 6, Spartan 6, and actually ML555 ML605 development board and the actual test. In addition, the board of control of the driver package, and provides user-level read and write a simple interface to facilitate the development of the top programs.
Platform: |
Size: 313344 |
Author: wu |
Hits:
Description: xilinx官方给的PCI Express DMA IP核的Linux下的驱动代码，以及代码文档-PCI Express DMA IP core of Linux driver code official to under xilinx, and code documentation
Platform: |
Size: 551936 |
Author: 徐小文 |
Hits: