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[VHDL-FPGA-Verilog] edge_detection

Description: edge detection algorithm in verilog HDL, along with test bench file. compiled in modelsim6.1
Platform: | Size: 34816 | Author: yahyajan | Hits:

[VHDL-FPGA-Verilog] sobel

Description: verilog sobel FPGA edge detection-Adopted verilog language realizes sobel edge detection in image processing algorithm
Platform: | Size: 10240 | Author: wkd | Hits:

[VHDL-FPGA-Verilog] Edge-detection

Description: 多个边缘检测sobel算子的verilog程序模块。-Multiple edge detection sobel operator verilog program modules
Platform: | Size: 4096 | Author: | Hits:

[VHDL-FPGA-Verilog] edge_tech_design

Description: verilog的边沿检测技术，在fpga信号处理中应用相当的大,这也是一门艺术-the the verilog edge detection technology, in fpga signal processing is quite large, and this is an art
Platform: | Size: 37888 | Author: 磨国钰 | Hits:

[VHDL-FPGA-Verilog] sobel

Description: 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)
Platform: | Size: 10222592 | Author: 丶大娱乐家 | Hits:

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