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[VHDL-FPGA-Verilog] mul_booth

Description: 基于BOOTH的32位快速乘法器的设计源码-BOOTH-based 32-bit fast multiplier design source
Platform: | Size: 2048 | Author: df | Hits:

[Other] e

Description: 《EDA技术实用教程》实验选编 专题一：计数分频器设计 4 专题二：存储器定制 7 实验一：快速乘法器电路设计 11 实验二：高速数字相关器设计 17 实验三：TLC5510高速A/D转换器控制 21 实验四：直接数字频率合成器（DDFS）设计 23 实验五：基于直接数字频率合成技术的任意波形发生器-" EDA technology practical course" Selected experimental one topic: the design count crossovers feature 4 2: 7 experiment a custom memory: Fast multiplier circuit design of 11 experiments II: the design of high-speed digital correlator 17, the experiment three: TLC5510 high-speed A/D converter control 21 of the experiment four: Direct Digital Frequency Synthesizer (DDFS) experimental design, 23 5: Based on Direct Digital Synthesis technology, arbitrary waveform generator
Platform: | Size: 2693120 | Author: 耿守浩 | Hits:

[VHDL-FPGA-Verilog] 65jie

Description: 串并FIR滤波器设计:并行FIR滤波器具有速度快、容易设计的特点，但是要占用大量的资源。在多阶数的亚高频系统设计中，使用并行结构并不合算，但亚高频系统需要较高的处理速度，而串行架构往往达不到要求，因此，结合串并这两种设计方法的长处，在使用较少的硬件资源的同时实现了较高的处理速度，这里说明一种65阶八路并行、支路串行FIR滤波器的设计（实际使用了1个乘法器，8个乘累加器，一个累加器）。-String and FIR filter design: parallel FIR filter with a fast, easy design features, but I want to use up a lot of resources. In a multi-order high-frequency sub-system design, the use of parallel structures and uneconomical, but the high frequency sub-system requires a higher processing speed, and the serial structure often fail, therefore, combines both the design of string and method' s strengths, using less hardware resources to achieve a high processing speed of 65 bands here that a parallel eight-way, slip serial FIR filter design (the actual use of a multiplier, 8 by accumulator, an accumulator).
Platform: | Size: 12288 | Author: 南才北往 | Hits:

[VHDL-FPGA-Verilog] lunwen

Description: 潘明海　刘英哲　于维双 (论文) 中文摘要： 本文讨论了一种可在FPGA上实现的FFT结构。该结构采用基于流水线结构和快速并行乘法器的蝶形处理器。乘法器采用改进的Booth算法，简化了部分积符号扩展，使用Wallace树结构和4-2压缩器对部分积归约。以8点复点FFT为实例设计相应的控制电路。使用VHDL语言完成设计，并综合到FPGA中。从综合的结果看该结构可在XC4025E-2上以52MHz的时钟高速运行。在此基础上易于扩展为大点数FFT运算结构。 -Pan Minghai Liuying Zhe Yu-dimensional pairs (thesis) Chinese Abstract: This paper discusses an FPGA can be implemented on the structure of the FFT. The architecture based on pipeline architecture and fast parallel multiplier butterfly processor. Multiplier using modified Booth algorithm simplifying the partial product sign extension, use the Wallace tree and 4-2 compressor for partial product reduction. 8-point complex-point FFT as an example design of the corresponding control circuit. To complete the design using the VHDL language, and integrated into the FPGA. From the results of a comprehensive look at the structure can be XC4025E-2 with 52MHz clock on the high-speed operation. On this basis, easy to expand the structure for large point FFT operations.
Platform: | Size: 128000 | Author: culun | Hits:

[VHDL-FPGA-Verilog] 8bit_mult

Description: 八位快速乘法器设计verilog HDL-8 bit Fast Multiplier Designverilog HDL
Platform: | Size: 47104 | Author: 孙世玮 | Hits:

[Software Engineering] doublemult

Description: 设计了一个双精度浮点乘法器。该器件采用改进的BOO TH 算法产生部分积, 用阵列和 树的混合结构实现对部分积的相加, 同时, 还采用了快速的四舍五入算法, 以提高乘法器的性能。把 设计的乘法器分为4 级流水线, 用FPGA 进行了仿真验证, 结果正确 并对FPGA 实现的时序结果 进行了分析。-Designed a double-precision floating-point multiplier. The device uses an improved algorithm for BOO TH generate part of the plot, with a mixed array and a tree structure to achieve the sum of the partial product, while also using a fast rounding algorithm to improve the performance of multipliers. The design of the multiplier is divided into four lines, carried out a simulation using FPGA verification result is correct and FPGA timing to achieve the results analyzed.
Platform: | Size: 209920 | Author: terry | Hits:

[DSP program] FFT_based_on_DSP

Description: 快速傅氏变换（FFT）是离散傅氏变换的快速算法，它是根据离散傅氏变换的奇、偶、虚、实等特性，对离散傅立叶变换的算法进行改进获得的。它对傅氏变换的理论并没有新的发现，但是对于在计算机系统或者说数字系统中应用离散傅立叶变换，可以说是进了一大步。数字信号处理器(DSP)是一种可编程的高性能处理器，近年来发展很快．它不仅适用于数字信号处理，而且在图像处理、语音处理、通信等领域得到了广泛的应用．通用的微处理器在运算速度上很难适应信号实时处理的要求．联沪处理器中集成有高速的乘法器硬件，能快速地进行大量数据的乘法和加法运算。快速傅里叶变换(FFT)的出现使得DFr在实际应用中得到了广泛的应用．-Fast Fourier Transform (FFT) is the Discrete Fourier Transform Algorithm, which is the discrete Fourier transform of the odd and even, true, real and other properties, on the discrete Fourier transform algorithm was modified to obtain. Fourier transform theory it is not a new discovery, but for the computer systems or digital systems using discrete Fourier transform, can be said that a big step into. Digital signal processor (DSP) is a programmable high-performance processor, developed rapidly in recent years. It is not only applicable to digital signal processing, and image processing, speech processing, communications and other fields has been widely used. General computing speed of microprocessors is difficult to adapt in real-time signal processing requirements. Contact Shanghai high-speed processor integrated hardware multiplier, can carry large amounts of data fast multiplication and addition operations. Fast Fourier Transform (FFT) of the DFR s emergence made in practical applic
Platform: | Size: 351232 | Author: Raymond | Hits:

[matlab] exact_alm_rpca

Description: RPCA (Robust Principal Component Analysis)是目前用于矩阵填充、图像去噪的最有效的优化方法。该代码是求解RPCA的一种数值算法——Exact ALM（Exact Augmented Lagrange Multiplier）-The most basic form of the exact ALM function is [A, E] = exact_alm_rpca(D, λ), and that of the inexact ALM function is [A, E] = inexact_alm_rpca(D, λ), where D is a real matrix and λ is a positive real number. We solve the RPCA problem using the method of augmented Lagrange multipliers. The method converges Q-linearly to the optimal solution. The exact ALM algorithm is simple to implement, each iteration involves computing a partial SVD of a matrix the size of D, and converges to the true solution in a small number of iterations. The algorithm can be further speeded up by using a fast continuation technique, thereby yielding the inexact ALM algorithm.
Platform: | Size: 380928 | Author: Bingmiao Huang | Hits:

[VHDL-FPGA-Verilog] 72

Description: 7:2乘法器 ，应用verilog语言 ，快速高效，使用了华莱士树-Dragging on time-multiplier, application verilog language, fast and efficient, the use of the Wallace tree
Platform: | Size: 8192 | Author: gaod | Hits:

[Industry research] Vhdl-Implementation-of--Fast-32x32-Multiplier-Bas

Description: The Vedic mathematics is quite different from conventional method of multiplication like adder and shifter. This mathematics is mainly based on sixteen principles. The multiplier (referred henceforth as Vedic multiplier) architecture based on the URDHVA TIRYAKBHYAM (Vertically and cross wise) sutra is presented. The existing method is 16*16 bit multiplication in relatively less speed. The proposed method is 32*32 bit multiplication in terms of relatively high speed, low power, less area and less delay. This will help in designing multiplier in VHDL, as its give effective utilization of structural method of modelling. This also gives chances for modular design where smaller block can be used to design the bigger one.-The Vedic mathematics is quite different from conventional method of multiplication like adder and shifter. This mathematics is mainly based on sixteen principles. The multiplier (referred henceforth as Vedic multiplier) architecture based on the URDHVA TIRYAKBHYAM (Vertically and cross wise) sutra is presented. The existing method is 16*16 bit multiplication in relatively less speed. The proposed method is 32*32 bit multiplication in terms of relatively high speed, low power, less area and less delay. This will help in designing multiplier in VHDL, as its give effective utilization of structural method of modelling. This also gives chances for modular design where smaller block can be used to design the bigger one.
Platform: | Size: 172032 | Author: farbosein | Hits:

[Industry research] Test_multiplier

Description: this is fast complex multiplier in vhdl
Platform: | Size: 1024 | Author: ste3191 | Hits:

[DSP program] book3e

Description: 数字信号处理的FPGA实现随书光盘，包含大量Verilog代码，包括加法器，乘法器以及FIR滤波器设计，快速傅立叶变换-FPGA digital signal processing to achieve the CD with the book, contains a large amount of Verilog code, including the adder, multiplier and FIR filter design, fast Fu Liye transform
Platform: | Size: 1870848 | Author: 刘许军 | Hits:

[VHDL-FPGA-Verilog] fast_radix10

Description: fpga implementation of fast radix 10 multiplier using verilog code
Platform: | Size: 3633152 | Author: karthick | Hits:

[Other] FastTVMMS

Description: 快速全变分和交替方向乘子法的程序FastTVMMS-Fast Total Variation and alternating directions multiplier method of procedure FastTVMMS
Platform: | Size: 116736 | Author: yangzhenzhen | Hits:

[Books] New-folder-(2)

Description: project-IMPLEMENTATION OF FAST SDC-SDF PIPELINED FFT USING CSD MULTIPLIER
Platform: | Size: 839680 | Author: Gowri shankar | Hits:

[Technology Management] gh

Description: IMPLEMENTATION OF FAST SDC-SDF PIPELINED FFT USING CSD MULTIPLIER
Platform: | Size: 839680 | Author: Gowri shankar | Hits:

[matlab] Water filling algorithm in MIMO

Description: Water-Filling (WF) is widely applied in power allocation in multichannel wireless communications. By mathematically linearising the optimal WF expression, the authors observe an intrinsic parallel-shift property of WF, based on which a fast and efficient WF algorithm is proposed. Compared with the conventional WF algorithms, it greatly simplifies WF execution by removing the Lagrange multiplier (or water-level) searching process.
Platform: | Size: 1516 | Author: Neelima | Hits:

[Other] 拉格朗日乘子法-fmincon

Description: 拉格朗日乘子法最优值求解，求解函数的最小值，极小值求解，求解速度快。效率高(The Lagrange multiplier method can solve the optimal value, the minimum value and the minimum value of the function, and the solution speed is fast. Efficient)
Platform: | Size: 10240 | Author: 冬瓜和鱼头 | Hits:

[Other] Comparative study of FFA architectures using different multiplier and adder topologies

Description: Parallel FIR filter is the prime block of many modern communication application such as MIMO, multi-point transceivers etc. But hardware replication problem of parallel techniques make the system more bulky and costly. Fast FIR algorithm (FFA) gives the best alternative to traditional parallel techniques. In this paper, FFA based FIR structures with different topologies of multiplier and adder are implemented. To optimize design different multiplication technique like add and shift method, Vedic multiplier and booth multiplier are used for computation. Various adders such as carry select adder, carry save adder and Han-Carlson adder are analyzed for improved performance of the FFA structure. The basic objective is to investigate the performance of these designs for the tradeoffs between area, delay and power dissipation. Comparative study is carried out among conventional and different proposed designs. The advantage of presented work is that; based on the constraints, one can select the suitable design for specific application. It also fulfils the literature gap of critical analysis of FPGA implementation of FFA architecture using different multiplier and adder topologies. Xilinx Vivado HLS tool is used to implement the proposed designs in VHDL.
Platform: | Size: 1123027 | Author: nalevihtkas | Hits:

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