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[Other resource] fifo数据缓冲器的vhdl源程序

Description: 编了个8*8位的fifo数据缓冲器的vhdl源程序，是经过quartusII4.2编译成功的程序。。希望能跟各位交流-Bianlegan 8 * 8 of the data buffer fifo VHDL source, after quartusII4.2 compiler successful procedures. . Hope you enjoy the exchanges
Platform: | Size: 1072 | Author: 夏社 | Hits:

[VHDL-FPGA-Verilog] 同步FIFO设计

Description: 用16*8 RAM实现一个同步先进先出（FIFO）队列设计。由写使能端控制该数据流的写入FIFO，并由读使能控制FIFO中数据的读出。写入和读出的操作由时钟的上升沿触发。当FIFO的数据满和空的时候分别设置相应的高电平加以指示。
Platform: | Size: 1302250 | Author: lavien520@163.com | Hits:

[VHDL-FPGA-Verilog] fifo数据缓冲器的vhdl源程序

Description: 编了个8*8位的fifo数据缓冲器的vhdl源程序，是经过quartusII4.2编译成功的程序。。希望能跟各位交流-Bianlegan 8* 8 of the data buffer fifo VHDL source, after quartusII4.2 compiler successful procedures. . Hope you enjoy the exchanges
Platform: | Size: 1024 | Author: 夏社 | Hits:

[VHDL-FPGA-Verilog] fifo88

Description: 8*8位的先入先出（fifo）数据缓冲器的vhdl源程序-8* 8 of the first-in-first out (FIFO) buffers the data source VHDL
Platform: | Size: 317440 | Author: hailaing | Hits:

[VHDL-FPGA-Verilog] fifo_01

Description: 8位相等比较器，比较8位数是否相等 -- 8-bit Identity Comparator -- uses 1993 std VHDL -- download from www.pld.com.cn & www.fpga.com.cn-eight other phase comparators, Comparing the same whether the median 8-- 8-bit Identity Comparator-- uses 1993 std VHDL-- download from www.pld.com.cn
Platform: | Size: 1024 | Author: 罗兰 | Hits:

[OS Develop] OSchunchu

Description: PAGES3完成了程序的 基本框架，FIFO()除了命中和置换情况外基本完成，但是修改位示图的子函数 出现问题，得不到正确的行数和列数，有时更改不了0 PAGES4修正了3中的问题，完成FIFO() PAGES5修正了FIFO()中执行置换时未将位示图中的对应块置0 PAGES6完成了LRU() PAGES7优化了界面，修正了切换算法后访问次数与上次算法相连的错误 PAGES8完成了OPT()修正了在页面置换切换时页表内存位示图不能各自初始化的错误。发现OPT（）中页面置换时出现的错误。 位示图置0和置1时出错 。而且输出的页表缺失项目 PAGES9好像是修正了 8中的错误，现在还没有找到让9中OPT()发生置换的测试用例 PAGES10找到8，9中出错原因，在于置换时没有得到最久要访问的Memory[i] PAGES11修正10中的错误。完成OPT() 发现了LRU()输出界面的信息冗余，已经更正 PAGES12删除了编程过程中的测试信息 PAGES13修正了判断溢出时的一个错误。将判断的〈=改为〈-PAGES3 completed a basic framework of the procedure, FIFO () except hit and replacement of the foreign basically completed, but changes Bitmap Functions of the problem, not the correct number of rows and columns, and sometimes change can PAGES4 amended 0 of 3, completed FIFO () PAGES5 amended the FIFO () implementation replacement failed to Bitmap the corresponding block home 0 PAGES6 completed the LRU () PAGES7 optimize the interface that the handoff algorithm with the number of visits after the last algorithm linked to the wrong PAGES8 completed the OPT () of the amendment pages replacement when switching memory page table Bitmap not their initialization errors. Found OPT () replacement pages at the mistakes. Bitmap home and home 0 errors 1:00. And the output page table missing items PAG
Platform: | Size: 10240 | Author: billdong | Hits:

[Other] buffervhdl

Description: 电子EDA,VHDL语言设计8位的fifo数据缓冲器的vhdl源程序-E-EDA, VHDL language design 8-bit data buffer fifo VHDL source code
Platform: | Size: 1024 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] 16×4bitFIFO

Description: 16×4bit的FIFO设计,VHDL语言编的的，能在ISE上仿真出来结果。-16 × 4bit the FIFO design, VHDL language series that can come out in the ISE on the simulation results.
Platform: | Size: 4096 | Author: 张军 | Hits:

[VHDL-FPGA-Verilog] FIFO_2

Description: VERILOG Synchronous FIFO. 4 x 16 bit words.-VERILOGSynchronous FIFO. 4 x 16 bit words.
Platform: | Size: 2048 | Author: likui | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.
Platform: | Size: 31744 | Author: yasir ateeq | Hits:

[VHDL-FPGA-Verilog] ram

Description: a 16 by 4 ram is used for many applications as a basic component such as fifo and stack etc
Platform: | Size: 1024 | Author: sri | Hits:

[VHDL-FPGA-Verilog] FIFO_8_8

Description: FIFO先进先出队列，一种缓存、或一种管道、设备、接口（Verilog HDL程序,内附说明）-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
Platform: | Size: 5120 | Author: 镜子 | Hits:

[VHDL-FPGA-Verilog] FIFOinterface

Description: fifo(8):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
Platform: | Size: 146432 | Author: sunbaoyu | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 512×8bid的FIFO 含工程文件，基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII
Platform: | Size: 4096 | Author: 邵捷 | Hits:

[VHDL-FPGA-Verilog] FIFO_Design

Description: 一种基于格雷码的异步FIFO设计与实现,8*8位的fifo VHDL 源码-Gray-code based on the Asynchronous FIFO Design and Implementation
Platform: | Size: 90112 | Author: qwe | Hits:

[VHDL-FPGA-Verilog] fifo

Description: fifo 的vhdl源程序,容量为1024*8的fifo程序代码-fifo the vhdl source code,Capacity of 1024* the fifo code 8
Platform: | Size: 1024 | Author: 谢文华 | Hits:

[OS Develop] FIFO

Description: 介绍了8*9FIFO功能及其用法，没有空满信号。-8* 9FIFO introduced the functions and usage, there is no full signal space.
Platform: | Size: 169984 | Author: qaz | Hits:

[VHDL-FPGA-Verilog] fifo89

Description: 先进先出FIFO缓冲器，8位字宽，9位字深，很简易的缓冲器。-FIFO FIFO buffer, 8-bit word wide, 9-bit words deep, very simple buffers.
Platform: | Size: 269312 | Author: gdfrg | Hits:

[VHDL-FPGA-Verilog] Synchronous FIFO

Description: 用16*8 RAM实现一个同步先进先出（FIFO）队列设计。由写使能端控制该数据流的写入FIFO，并由读使能控制FIFO中数据的读出。写入和读出的操作由时钟的上升沿触发。当FIFO的数据满和空的时候分别设置相应的高电平加以指示(mplementation of a synchronous first in first out (FIFO) queue design with 16*8 RAM. A write FIFO that controls the data stream by writing enable terminals and controls read of data in the FIFO by the read enable. The operation of writing and reading is triggered by the rising edge of the clock. When the data of FIFO is full and empty, set the corresponding high level to indicate)
Platform: | Size: 264192 | Author: 渔火 | Hits:

[VHDL-FPGA-Verilog] Router fifo for NOC

Description: Router 8-bit fifo design, written in Verilog
Platform: | Size: 822 | Author: spgp1306 | Hits:
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