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[Books] 32bits_float_muliplier

Description: 32位浮点乘法器的设计，讲的挺好的，供参考啊-32-bit floating-point multiplier design, speak very good, and for reference ah
Platform: | Size: 97280 | Author: downloader | Hits:

[VHDL-FPGA-Verilog] fadd

Description: 6级流水，verilog实现浮点数的加法，其中浮点数格式符合IEEE754标准-6 water, verilog realize the floating point adder, in which floating-point format in line with the IEEE754 standard
Platform: | Size: 2048 | Author: 兰兰 | Hits:

[Algorithm] multiply

Description: 这是我用verilog hdl语言写的浮点乘法器,用的是基4的booth算法,对于部分积使用了5-2压缩和3-2压缩,欢迎大家指点,也欢迎大家把它改成流水线以提高速度.-This is my verilog hdl language used to write floating-point multiplier, using a Radix-4 algorithm for the booth for part of the plot using the 5-2 and 3-2 compression compression, welcomed everyone pointing, also welcomed the U.S. put it into a pipeline to improve speed.
Platform: | Size: 4096 | Author: lanty | Hits:

[VHDL-FPGA-Verilog] CourseDesign

Description: 用Verilog实现一位原码浮点数乘法器，按照累加的方式，逐位相乘，再相加。-Verilog realization of an original code with floating point multiplier, in accordance with the cumulative way, bit by bit multiply, then add.
Platform: | Size: 245760 | Author: 李伟彬 | Hits:

[VHDL-FPGA-Verilog] floating-point-multiplier

Description: verilog implementation of the floating point multiplier
Platform: | Size: 1024 | Author: ramtin | Hits:

[VHDL-FPGA-Verilog] mult

Description: 32位浮点乘法器的源代码，用verilog来实现的-32-bit floating point multiplier source code to achieve with verilog
Platform: | Size: 2048 | Author: yolin | Hits:

[VHDL-FPGA-Verilog] MULT

Description: the document used to describe the verilog codes design floating point multiplier in coms design
Platform: | Size: 2351104 | Author: rajapraba | Hits:

[VHDL-FPGA-Verilog] Floating-Point-Multiplier-in-Verilog

Description: Floating Point Multiplier in Verilog
Platform: | Size: 64512 | Author: Khalid Nawaz Khan | Hits:

[VHDL-FPGA-Verilog] Mul32

Description: Verilog语言编写的单精度浮点数乘法器-The Verilog language of single precision floating point multiplier
Platform: | Size: 8192 | Author: lenovo | Hits:

[VHDL-FPGA-Verilog] altfp_mult_abs

Description: 浮点数 乘法器带绝对值运算 verilog语言编写 可直接调用-Floating-point multiplier verilog language with absolute operation can be called directly
Platform: | Size: 324608 | Author: linyi | Hits:

[VHDL-FPGA-Verilog] floating-point-multip

Description: verilog code for floating point multiplier
Platform: | Size: 51200 | Author: rajesh | Hits:

[Other] 基于FPGA的单精度浮点数乘法器设计

Description: 《基于FPGA的单精度浮点数乘法器设计》详细介绍了按照IEEE754标准在FPGA上实现单精度浮点加减乘除的方法(The design of single precision floating point multiplier based on FPGA introduces in detail the way of realizing single precision floating point addition, subtraction and multiplication and division based on IEEE754 standard on FPGA.)
Platform: | Size: 2432000 | Author: sisuozheweilai | Hits:

[Other] Fixed-Floating-Point-Adder-Multiplier-master

Description: Fixed-Floating-Point-Adder-Multiplier with test bench
Platform: | Size: 9216 | Author: liki20 | Hits:

[VHDL-FPGA-Verilog] float_mult32x32.v

Description: verilog 语言写的FPGA内部实现硬件浮点乘法器的源码，两个时钟周期完成一次浮点乘法运算(The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock cycles.)
Platform: | Size: 1024 | Author: orangell | Hits:

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