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[VHDL-FPGA-Verilog] FPGA_SUM99_VHDL_SOURCE DL : 0: 基于FPGA的直接数字合成器的设计与分析的代码程序,代码格式为VHDL-FPGA-based Direct Digital Synthesis Design and Analysis of the code procedures for VHDL code format
Update : 2025-02-17 Size : 5kb Publisher : 莫汉伟
[Communication] Project1-DDS DL : 0: 直接频率和成DDS，可以在Altera的FPGA下载实现-directly into DDS frequency and can be downloaded from Altera FPGA Implementation
Update : 2025-02-17 Size : 8kb Publisher : lf
[VHDL-FPGA-Verilog] DDS DL : 0: 用51和 FPGA实现的 DDS的程序-FPGA with 51 and realize the process of DDS
Update : 2025-02-17 Size : 5kb Publisher : 胡玉贵
[Communication-Mobile] DDFS_PLL_10DA_with51 DL : 0: FPGA下的DDS程序的编写,VHDL语言,-FPGA under DDS preparation procedures, VHDL language,
Update : 2025-02-17 Size : 613kb Publisher : huang
[VHDL-FPGA-Verilog] msp430_jtag_nios DL : 0: 将msp430与使用nios的fpga相连，将fpga作为msp430的jtag使用。其中用到了nios内的多种接口以及dma操作-The MSP430 with the use of the Nios FPGA connected to the FPGA as the MSP430 JTAG to use. Which used the Nios multiple interfaces and dma operation
Update : 2025-02-17 Size : 55kb Publisher : danielmu
[VHDL-FPGA-Verilog] dds DL : 0: DDS正弦信号发生器频率和相位连续可调。频率最大2M
Update : 2025-02-17 Size : 3kb Publisher : dsf
[VHDL-FPGA-Verilog] dds DL : 0: 利用fpga实现的DDS，可输出正弦波，输出频率可调-FPGA realization of the use of DDS, sine wave output, output frequency adjustable
Update : 2025-02-17 Size : 458kb Publisher : qlg
[Wavelet] DDS DL : 0: 利用EDA技术和FPGA在UP3开发板上实现直接数字频率综合器的设计。实验中加入了相位控制字PWORD，用以控制相位偏移量的前四位，将相位偏移量加到ROM地址总线上，从而引起从ROM中取得的正弦信号的偏移，实现移相信号发生器的移相功能。实验中还加入了LCD显示功能，通过LCD显示模块器件，用LCD显示正弦信号的频率，所显示的频率也是由频率字控制的。LCD的驱动原理同上次实验。-The use of EDA technology and FPGA development in the UP3 board direct digital frequency synthesizer design. Experiment by adding a phase control word PWORD, to control the phase offset of the top four will be added to the phase offset ROM address bus, thereby causing ROM obtained from the sinusoidal signal offset, shifted believe realize its phase-shifting function generator. Experiments have also joined the LCD display, LCD display module through the device, with LCD display the frequency of sinusoidal signal, as shown by the frequency of word frequency control. LCD driving principles with the previous experiment.
Update : 2025-02-17 Size : 1.17mb Publisher : Emma
[VHDL-FPGA-Verilog] vhdl-dds DL : 0: fpga 控制dds 程序。希望对各位有用-dds FPGA control procedures. Members wish to be useful
Update : 2025-02-17 Size : 86kb Publisher : martin
[VHDL-FPGA-Verilog] dds DL : 0: 基于VHDL+FPGA的DDS信号发生设计，已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode
Update : 2025-02-17 Size : 547kb Publisher : 陈阳
[Software Engineering] DDS DL : 0: 基于DDS原理的正弦信号发生器。用VERILOG语言实现，功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
Update : 2025-02-17 Size : 545kb Publisher : 毛华站
[Software Engineering] dds DL : 0: 基于FPGA的双路可移相任意波形发生器 Altera中国大学生电子设计文章竞赛获奖作品刊登-FPGA-based dual phase shifter can be arbitrary waveform generator Altera China Undergraduate Electronic Design Contest winning entries published articles
Update : 2025-02-17 Size : 1.62mb Publisher : 姜兆刚
[VHDL-FPGA-Verilog] FPGA DL : 0: FPGA，vhdl语言的学习资料； FPGA的简单设计 dds的设计-FPGA, vhdl language learning materials FPGA design of a simple design dds
Update : 2025-02-17 Size : 2mb Publisher : wade
[Books] dds DL : 0: FPGA实现DDS，f=90kHZ~5MHZ范围-FPGA realization of DDS, f = 90kHZ ~ 5MHZ the scope of
Update : 2025-02-17 Size : 1.38mb Publisher : 王勤
[VHDL-FPGA-Verilog] DDS DL : 0: 自己在Quartus下用VHDL编写的一个DDS程序。包括寄存器，累加器，波形存储器-In Quartus using VHDL procedures for the preparation of a DDS. Including the register, accumulator, waveform memory
Update : 2025-02-17 Size : 343kb Publisher : ice
[VHDL-FPGA-Verilog] dds DL : 0: fpga利用dds原理，产生正弦波，简单实用，成本低-fpga using dds principle, have a sine wave
Update : 2025-02-17 Size : 558kb Publisher : wangjian
[Program doc] FPGA-DDS-FM DL : 0: DDS 调频信号发生器框图设计原理，有仿真测试结果-DDS signal generator FM Design Principle diagram
Update : 2025-02-17 Size : 68kb Publisher : chenjiwei
[VHDL-FPGA-Verilog] FPGA-DDS DL : 1: 在FPGA内，以查表方式实现频率直接合成器（DDS）功能。verilog源代码-In the FPGA in order to achieve the look-up table means the direct synthesizer frequency (DDS) feature. verilog source code
Update : 2025-02-17 Size : 2kb Publisher : niuqs
[VHDL-FPGA-Verilog] DDS-FPGA DL : 0: 基于FPGA的DDS资料！个人搜集的可直接编译-FPGA-based DDS information!
Update : 2025-02-17 Size : 6.06mb Publisher : eva
[VHDL-FPGA-Verilog] DDS DL : 0: 毕业设计，基于FPGA的DDS设计与实现模块-FPGA DDS
Update : 2025-02-17 Size : 2.33mb Publisher : 钟志强

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