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[VHDL-FPGA-Verilog] 基于FPGA的直接数字合成器设计

Description: 1、 利用FLEX10的片内RAM资源，根据DDS原理，设计产生正弦信号的各功能模块和顶层原理图； 2、 利用实验板上的TLC7259转换器，将1中得到的正弦信号，通过D/A转换，通过ME5534滤波后在示波器上观察； 3、 输出波形要求： 在输入时钟频率为16KHz时，输出正弦波分辨率达到1Hz； 在输入时钟频率为4MHz时，输出正弦波分辨率达到256Hz； 4、 通过RS232C通信，实现FPGA和PC机之间串行通信，从而实现用PC机改变频率控制字，实现对输出正弦波频率的控制。-a use FLEX10-chip RAM resources, in accordance with DDS principle, design sinusoidal signal generated by the top-level functional modules and schematics; 2, the experimental board TLC7259 converters, will be a sinusoidal signal, the D/A conversion, after filtering through the ME5534 oscilloscope observation; 3, the output waveform requirements : the input clock frequency of 16KHz, sine wave output resolution of 1Hz; the input clock frequency of 4MHz, the sine wave output resolution of 256Hz; 4, RS232C communications, FPGA and PC serial communications between in order to achieve PC-frequency control characters, the realization of sine wave output frequency control.
Platform: | Size: 21504 | Author: 竺玲玲 | Hits:

[VHDL-FPGA-Verilog] DDS_Power

Description: FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.
Platform: | Size: 16384 | Author: 田世坤 | Hits:

[VHDL-FPGA-Verilog] ram

Description: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Platform: | Size: 2048 | Author: nick | Hits:

[Other Embeded program] epp_sram

Description: verilog语言编写的FPGA代码。功能为pc机通过epp不断写数到sram中，然后pc发送中断信号打断写过程读取sram中的数据。rar包中包含epp协议，模块文件和测试文件（test）。-Verilog FPGA code languages. Pc machine functions through a number of epp constantly write to the SRAM, and then pc send interrupt signals to interrupt the process of writing to read the data in the SRAM. rar package includes epp agreement, modules and test documents (test).
Platform: | Size: 43008 | Author: 苗苗 | Hits:

[VHDL-FPGA-Verilog] FPGA_write_sram

Description: FPGA向SRAM中写入数据，VHDL编程-FPGA to the SRAM write data, VHDL programming
Platform: | Size: 262144 | Author: 简 | Hits:

[MiddleWare] ram

Description: fpga中ram的vhdl的经典程序，适用于ALTERA公司器件-FPGA in VHDL ram the classic procedure, applicable to the company ALTERA devices
Platform: | Size: 1024 | Author: gcy | Hits:

[Software Engineering] FPGA_SDR_Sdram_LED

Description: 针对主控制板上存储器(SRAM) 存储的数据量小和最高频率低的情况,提出了基于SDR Sdram(同步动态RAM) 作为主存储器的LED 显示系统的研究。在实验中,使用了现场可编程门阵列( FPGA) 来实现各模块的逻辑功能。最终实现了对L ED 显示屏的控制,并且一块主控制板最大限度的控制了256 ×128 个像素点,基于相同条件,比静态内存控制的面积大了一倍,验证了动态内存核[7 ]的实用性。-For the main control board memory (SRAM) a small amount of stored data and the highest frequency of low, based on SDR Sdram (Synchronous Dynamic RAM) as the main memory of the LED display systems. In the experiment, the use of field programmable gate array (FPGA) to realize the logic function of each module. The eventual realization of L ED display control, and a master control panel to maximize the control of the 256 × 128 pixels point, based on the same conditions than the static memory control area has doubled, to verify the dynamic memory of nuclear [7 ] the practicality.
Platform: | Size: 510976 | Author: 郑宏超 | Hits:

[Other] my_ram_vhdl

Description: how to infer ram for fpga altera xilinx
Platform: | Size: 1024 | Author: yusuf.abdullah | Hits:

[VHDL-FPGA-Verilog] FPGA-SRAMt-test

Description: 测试型号为EP2C5Q208C8的FPGA的RAM是否正常，按提示操作，并显示每步的测试结果-EP2C5Q208C8 test models for the FPGA' s RAM and whether it is normal, according to prompts, and display each step of the test results
Platform: | Size: 2048 | Author: 冀少威 | Hits:

[VHDL-FPGA-Verilog] ram_Test

Description: RAM读写控制器，用verilog实现的简单易懂的RAMROMsram控制核-Controller RAM read and write, using verilog implementation of easy-to-understand control of nuclear RAMROMsram
Platform: | Size: 3072 | Author: 王欢 | Hits:

[VHDL-FPGA-Verilog] RS232capture

Description: This approach, we feel, came very close to obtaining an image from the camera OV7620. Before we tried to capture a camera signal, we successfully transferred a test image from the FPGA s onboard RAM modules through RS232 to the PC program. This file do it.
Platform: | Size: 39936 | Author: Joelmir J Lopes | Hits:

[VHDL-FPGA-Verilog] ram

Description: ram的vhdl源代码在colloy实现-ram in the vhdl source code to achieve colloy
Platform: | Size: 1920000 | Author: mamou | Hits:

[TCP/IP stack] stackfiles

Description: VHDL IP Stack: This IP stack for an FPGA is a complex design because of the number of layers and the complexity of each that is required. It is limited to 10Mb/s operation and is designed for a full duplex switched network. It implements the lower layers of a standard TCP/IP stack. Further implementation is needed to make it work specifically for a certain purpose (eg a web server). There is support to read and write to RAM from the PC via the parallel port as well, for debugging and tests purposes (this maybe easily removed). Note the design only supports IP and ARP frames, other protocols such as RARP and 802.2 frames are not supported.-VHDL IP Stack: This IP stack for an FPGA is a complex design because of the number of layers and the complexity of each that is required. It is limited to 10Mb/s operation and is designed for a full duplex switched network. It implements the lower layers of a standard TCP/IP stack. Further implementation is needed to make it work specifically for a certain purpose (eg a web server). There is support to read and write to RAM from the PC via the parallel port as well, for debugging and tests purposes (this maybe easily removed). Note the design only supports IP and ARP frames, other protocols such as RARP and 802.2 frames are not supported.
Platform: | Size: 81920 | Author: James | Hits:

[VHDL-FPGA-Verilog] TLC5510_IIPRAM1

Description: FPGA控制双口RAM、实现TLC5510采样控制双口RAM读写！QUARTUS II8.0平台仿真验证通过，并在硬件上运行通过测试！-FPGA control of dual-port RAM, the realization of sampled-data control TLC5510 dual-port RAM read and write! QUARTUS II8.0 platform through simulation and hardware to run through the test!
Platform: | Size: 3439616 | Author: wangzhaohui | Hits:

[ARM-PowerPC-ColdFire-MIPS] ram

Description: 用FPGA做的RAM，源码，调试通过，有工程-FPGA to do with RAM, source code, debugging through, there are works
Platform: | Size: 452608 | Author: 马泽龙 | Hits:

[VHDL-FPGA-Verilog] ram

Description: 使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个RAM存储器。-The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a RAM memory.
Platform: | Size: 198656 | Author: Daisy | Hits:

[Other Embeded program] ARM-read-FPGA-data1.7

Description: ARM读取从FPGA双口RAM读取AD采样1.7-ARM FPGA dual-port RAM read to read from the AD sample 1.7
Platform: | Size: 1360896 | Author: 张鹏 | Hits:

[source in ebook] Dual-RAM

Description: DSP EMIF双口RAM和FPGA实现高速通信-DSP EMIF dual-port RAM and FPGA to achieve high-speed communications
Platform: | Size: 573440 | Author: lerning dog | Hits:

[VHDL-FPGA-Verilog] F0501

Description: 汽车VCU控制器测试工装的程序，STM32单片机扩展总线读写FPGA内部RAM，DDS方式产生PWM，PWM频率，脉宽测量功能(Automotive VCU controller test tooling procedures, STM32 microcontroller expansion bus read and write FPGA, the internal RAM, DDS way to generate PWM, PWM frequency, pulse width measurement function)
Platform: | Size: 7674880 | Author: nan211 | Hits:

[VHDL-FPGA-Verilog] fpga

Description: pid算法控制电机运动，实现fpga与dsp的双口RAM通信(PID algorithm to control motor movement, the realization of FPGA and DSP dual port RAM communication)
Platform: | Size: 13411328 | Author: 峰语 | Hits:
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