Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - fpga vhdl project

Search list

[Embeded-SCM Develop] DDSforsinandcos

Description: 用VHDL实现的DDS，可输出正弦、余弦波形。将所有文件放在一个工程文件里，再分别生存模块，按原理图连接及可-using VHDL DDS, output sine, cosine wave. All documents will be placed on a project document, respectively survival module, according to diagram and can link
Platform: | Size: 7168 | Author: 何明均 | Hits:

[VHDL-FPGA-Verilog] FPGA-based_oscilloscope

Description: FPGA-based_oscilloscope,VHDL写的实现 示波器的程序，及完整的工程描述文档-FPGA-based_oscilloscope. VHDL was oscilloscope to achieve the realization of the process, and complete the project description document
Platform: | Size: 228352 | Author: 严刚 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 串口通讯协议，你您可以自己建个工程，再将需要的VHDL文本，添加到工程中，理解程序在仿真！-Serial communication protocol, you can build your project, and then need VHDL text, added to the project, understand the procedures in the simulation!
Platform: | Size: 10240 | Author: 张亚伟 | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: FPGA设计全流程：Modelsim>>Synplify.Pro>>ISE 第一章 Modelsim编译Xilinx库 第二章 调用Xilinx CORE-Generator 第三章 使用Synplify.Pro综合HDL和内核 第四章 综合后的项目执行 第五章 不同类型结构的仿真-FPGA design of the whole process: Modelsim>> Synplify.Pro>> ISE Chapter ModelSim Xilinx compiler library chapter called Xilinx CORE-Generator Chapter III Synplify.Pro integrated use of Chapter IV of HDL and kernel integrated implementation of the project after the Chapter V structure of different types of simulation
Platform: | Size: 218112 | Author: 青岚之风 | Hits:

[Other] FPGAmanual

Description: 这是自己在做毕业设计时，导师给的一些参考书，觉得还不错，希望对于那些FPGA编程爱好者有所帮助！-This is his graduation project to do, the mentor to a number of reference books, feel good, I hope for those who help FPGA programming enthusiasts!
Platform: | Size: 1916928 | Author: shengm1 | Hits:

[VHDL-FPGA-Verilog] mmcfpgaconfig.tar

Description: 基于FPGA的MMC卡实现，内部包含了C++仿真调试代码以及FPGA的实现代码，建立工程后可以之间编译调试-FPGA-based MMC card, Internal contains C++ Simulation debugging code, as well as the realization of FPGA code, the establishment of the project can be between the compiler debugging
Platform: | Size: 7168 | Author: 王弋妹 | Hits:

[USB develop] USB

Description: 这个工程是基于FPGA与Philips的D12 USbB 1.1的完整设计，包括VHDL驱动和主机应用程序及驱动-The project is based on FPGA and Philips of the D12 USbB 1.1 complete design, including VHDL-driven and mainframe applications and drivers
Platform: | Size: 2749440 | Author: Phirix Shaw | Hits:

[Other] lcd1602

Description: FPGA工程文件 通过FPGA在LCD上显示“this is my frist program"的字体 已经验证，供大家学习使用。-FPGA through the FPGA project file in the LCD display
Platform: | Size: 630784 | Author: 马亮 | Hits:

[VHDL-FPGA-Verilog] DA_FIR

Description: 基于分布式算法的FPGA实现的FIR滤波器源码，VHDL语言编写的，下载工程文件后可直接在QuartusII7.0上运行。-Based on Distributed algorithms realize the FIR filter FPGA source code, VHDL language, download the project file can be run directly in QuartusII7.0.
Platform: | Size: 531456 | Author: CH | Hits:

[VHDL-FPGA-Verilog] flowled

Description: FPGA开发入门的Verilog HDL程序---流水灯,真实可用，验证通过，工程环境为Altera Quartus -FPGA development of Verilog HDL entry procedures- water lights, the real available, authentication is passed, the project environment for Altera Quartus
Platform: | Size: 193536 | Author: renyong0801 | Hits:

[VHDL-FPGA-Verilog] uart_ise_vhdl

Description: fpga里实现 uart 经典 vhdl语言写的 ise工程文件-fpga implementation in vhdl language classic uart of ise project file
Platform: | Size: 22528 | Author: 孙俪 | Hits:

[VHDL-FPGA-Verilog] clk_vhdl

Description: Quartus II工程压缩文件，是一个典型的基于FPGA的数字钟工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. Using VHDL language.
Platform: | Size: 652288 | Author: kg21kg | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: Quartus II工程压缩文件，是一个典型的基于FPGA的秒表工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based project of the stopwatch, a 50MHz frequency, counting, decoding modules. Using VHDL language.
Platform: | Size: 464896 | Author: kg21kg | Hits:

[VHDL-FPGA-Verilog] Electronic_Calendar_Based_On_FPGA

Description: 本项目主要是利用FPGA技术实现电子日立的功能，显示年月日星期，显示格式为：“年. 月. 日. 星期”，其中年月日星期均为可调电路。该项目共有七个模块：星期控制电路、日期控制电路、月份控制电路、年份控制电路、选择月份电路、扫描显示电路和调节电路。总体思路是：星期和日期控制电路共用一个脉冲信号；日期的进位反馈给调节电路，再通过调节电路中的开关控制选择月份和月份控制电路的脉冲信号，以起到随时调节月份的作用；同理，月份控制电路的进位反馈给调节电路以随时调节年份。-The project is mainly the use of FPGA technology to achieve the functions of e-Hitachi, showing date week display format: "year. On. Day. Weeks", which are adjustable date-week circuit. A total of seven modules of the project: week control circuit, the date of the control circuit, control circuit of the month, year, control circuit, select the month of the circuit, scan display circuit and regulating circuit. The general idea is: the date a week and share a pulse control circuit signal date back to the binary-conditioning circuit, and then by adjusting the switch control circuit to choose the month and the month of the pulse signal control circuit, at any time to play a role in regulation of the month with the rationale for, the month of binary control circuit to adjust the feedback circuit to adjust the year at any time.
Platform: | Size: 43008 | Author: xiaoxu | Hits:

[VHDL-FPGA-Verilog] Fingerprint_Identify

Description: 本项目名称是：基于FPGA的指纹识别模块设计。 主要内容为：本模块采用xilinx公司的Spartan 3E系列XC3S500E 型FPGA作为核心控制芯片，通过富士通公司的MFS300滑动式电容指纹传感器对指纹图象进行提取，然后对提取的指纹图像进行灰度滤波、图像增强、二值化、二值去噪、细化等预处理，得到清晰的指纹图象，再从清晰的指纹图象中提取指纹特征点，存入外部FLASH作为建档模板。指纹比对时，采用同样的方法获得清晰的指纹图像，建立比对模板，然后将比对模板与建档模板利用点模式匹配算法进行比对，得出比对结果。该模块利用嵌入式软核实现系统的管理，利用硬件实现指纹识别，保证了系统功能的完整性与识别的正确性。该识别模块可用于门禁、考勤、安检、保险箱柜等很多方面，也可和计算机等设备联机使用，满足各个方面的不同需求，因此它的设计具有很广泛的应用前景和市场价值。 -The project name is: FPGA-based fingerprint identification module design. The main contents are: the use of this module xilinx s Spartan 3E Series XC3S500E FPGA-based control chip as the core, through the MFS300 Fujitsu fingerprint slide sensor capacitance extraction of the fingerprint image, and then extracted gray-scale fingerprint image filtering, image enhancement, binarization, denoising Second, refinement, etc. pre-treatment have been given clear fingerprint image, and then a clear fingerprint image from the extracted fingerprint feature points, into the external FLASH file as a template. Fingerprint matching using the same method to obtain a clear image of the fingerprint to establish than the template, and then will be the template file templates and the use of point pattern matching algorithm than the right, than the results obtained. The module is the realization of the use of soft-core embedded system management, the use of fingerprint recognition hardware implementation
Platform: | Size: 191488 | Author: xiaoxu | Hits:

[Software Engineering] tetris

Description: Our project is to design and implement a Tetris game by using FPGA. Tetris a puzzle game that uses 4 square blocks joining edge to edge to form various combinations of shapes. There are 7 unique shapes. The shapes are controlled with the arrow keys from keypad or joystick. Both keypad and joystick are used to control the rotation of the shape. The reason we use both keypad and joystick as controller tool is that the players can have two options to control the game conveniently. However, we may use either keypad or joystick in our presentation to make the best effect. -Our project is to design and implement a Tetris game by using FPGA. Tetris is a puzzle game that uses 4 square blocks joining edge to edge to form various combinations of shapes. There are 7 unique shapes. The shapes are controlled with the arrow keys from keypad or joystick. Both keypad and joystick are used to control the rotation of the shape. The reason we use both keypad and joystick as controller tool is that the players can have two options to control the game conveniently. However, we may use either keypad or joystick in our presentation to make the best effect.
Platform: | Size: 5120 | Author: krishna | Hits:

[VHDL-FPGA-Verilog] Vme_Interface

Description: 这是本人设计的一个关于VME总线接口的FGPA程序，FPGA一边连接ARM LPC2294，一边连接VME总线，FPGA采用的XILINX公司的SPARTANII系列，程序包包含完整的工程文件-This is my design of a VME bus interface on the FGPA procedures, FPGA side of the connection ARM LPC2294, while connecting VME bus, FPGA using the XILINX Inc. SPARTANII series, the package contains a complete project file
Platform: | Size: 2688000 | Author: zhangsongbai | Hits:

[VHDL-FPGA-Verilog] traffic_light

Description: this project is traffic lights on fpga. ı used xilinx ise and simulated modelsim. [used spartan 3e development kit]. -this project is traffic lights on fpga. ı used xilinx ise and simulated modelsim. [used spartan 3e development kit].
Platform: | Size: 657408 | Author: ali | Hits:

[VHDL-FPGA-Verilog] FPGA_examples

Description: FPGA工程例子.verilog HDL语言编写；-FPGA project examples. Verilog HDL language
Platform: | Size: 3441664 | Author: 严成 | Hits:

[VHDL-FPGA-Verilog] led_water

Description: Altera FPGA流水灯工程文件Verilog语言代码，作为入门级的参考程序-Altera FPGA Verilog flow light project files language code, as the entry-level reference program
Platform: | Size: 234496 | Author: kiling | Hits:
« 12 3 4 5 6 »

CodeBus www.codebus.net