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[VHDL-FPGA-Verilog] COUNTER

Description: 对外部输入的高频脉冲信号进行分频，应用于FPGA/CPLD .-External input of high-frequency pulse signal frequency, applies to FPGA/CPLD.
Platform: | Size: 1024 | Author: fsdfe | Hits:

[VHDL-FPGA-Verilog] counter

Description: 用Verilog HDL语言实现FPGA的频率等精度测量。（已经过验证）-Using Verilog HDL language, such as FPGA frequency measurement accuracy. (Has already been verified)
Platform: | Size: 2582528 | Author: double | Hits:

[VHDL-FPGA-Verilog] ADC_Fre_counter_LED_keyboard

Description: FPGA tlc082０采样控制　高精度测频　ＬＥＤ键盘显示　ＶＨＤｌ　调试与ＥＰ１Ｃ３-FPGA vhdl ADC LED keyboard frequency counter test
Platform: | Size: 2595840 | Author: Albert Sun | Hits:

[VHDL-FPGA-Verilog] FPGA_Counter

Description: 利用FPGA设计的可以自适应的频率计，里面有详细的文档介绍。-FPGA designs can use adaptive frequency counter, which document describes in detail.
Platform: | Size: 106496 | Author: 李庆雨 | Hits:

[Embeded-SCM Develop] DigitalClock

Description: 基于FPGA的数字电子钟设计，系统总程序由分频模块、“时分秒”计数器模块、数据选择模块、报时模块、动态扫描显示和译码模块组成。得到一个将“时”、“分”、“秒”显示于人的视觉器官的计时装置。它的计时周期为24小时，显示满刻度为23时59分59秒，另外有校时、校分和整点报时功能，并通过数码管驱动电路显示计时结果。-FPGA-based design of digital electronic clock, the system program by the total frequency module, " the minutes and seconds" counter module, data selection module, timer module, dynamic scanning display and decoding module. Get a will " ," and " division" and " seconds" display on the human visual organ of the timing device. It' s time for the 24-hour period, indicating full scale as 23:59:59, and another school, the school hours and the whole hour, and through digital tube display driver circuit timing results.
Platform: | Size: 63488 | Author: sunnan | Hits:

[VHDL-FPGA-Verilog] Fre_Counter_verilog

Description: 基于ep3c25的FPGA频率计的简单设计（用verilog HDL），直接打开即可-FPGA frequency counter based on ep3c25 of simple design (using verilog HDL), can directly open the ... ...
Platform: | Size: 1138688 | Author: yunhen | Hits:

[VHDL-FPGA-Verilog] Frequency_Counter

Description: 基于ep3c25的FPGA频率计的简单设计（用VHDL编写），直接打开即可-FPGA frequency counter based on ep3c25 of simple design (using VHDL written), directly open a can ... ...
Platform: | Size: 1130496 | Author: yunhen | Hits:

[VHDL-FPGA-Verilog] plj

Description: 此程序为fpga的频率计vhdl程序,功能是可以检测到输入信号的频率并且通过八位数码管显示-This procedure is the frequency counter vhdl fpga program function is to detect the frequency of the input signal and the digital display by eight
Platform: | Size: 561152 | Author: 宫晓鹏 | Hits:

[VHDL-FPGA-Verilog] Clk50M_div_1HZ

Description: Clk50M_div_1HZ，调试已通过，采用计数器分频 此实验采用计数器，将板载的50MHz时钟源分频为1Hz，分频的结果以LED灯的形式显示。下载电路至FPGA后，会发现LED0会以1Hz的频率闪动。-Clk50M_div_1HZ, using counter this study, frequency counter, onboard 50MHz clock frequency of 1Hz, frequency results in the form of LED lights display. Download the circuit to the FPGA, you will find LED0 will be the frequency of 1Hz flashing.
Platform: | Size: 324608 | Author: 王晨 | Hits:

[VHDL-FPGA-Verilog] counter

Description: 本文介绍了基于FPGA的数字频率计的设计方法，设计采用硬件描述语言Verilog ，在软件开发平台ISE上完成，可以在较高速时钟频率（48MHz）下正常工作。该数字频率计采用测频的方法，能准确的测量频率在10Hz到100MHz之间的信号。-This article describes the FPGA-based digital frequency meter design method using hardware description language Verilog, ISE on the complete software development platform, can be compared with high-speed clock frequency (48MHz) to work properly. The digital frequency meter using frequency measurement method, can accurately measure the frequency of the signal between 10Hz to 100MHz.
Platform: | Size: 1880064 | Author: PengJ | Hits:

[VHDL-FPGA-Verilog] 8-bit-decimal-frequency-meter

Description: 利用FPGA，实现8位十进制频率计功能。高效，实用。-Using FPGA, to achieve 8-bit decimal frequency counter function. Efficient and practical.
Platform: | Size: 307200 | Author: 云龙 | Hits:

[VHDL-FPGA-Verilog] Frequency-counter

Description: 基于FPGA的频率计设计。通过FPGA运用、 HDL编程，利用FPGA(现场可编程门阵列)芯片设计了一个8位数字式等精度频率计，该频率计的测量范围为0-100MHZ，利用QUARTUS II集成开发环境进行编辑、综合、波形仿真，并下载到CPLD器件中，经实际电路测试，仿真和实验结果表明，该频率计有较高的实用性和可靠性。-Frequency counter FPGA-based design. By using FPGA, VHDL programming, the use of FPGA (field programmable gate array) chip design an 8-bit digital precision frequency meter, etc., the frequency meter measurement range of 0-100MHZ, using QUARTUS II integrated development environment for editing, synthesis, simulation waveforms, and downloaded to the CPLD device, the actual circuit testing, simulation and experimental results show that the frequency counter has a higher availability and reliability.
Platform: | Size: 595968 | Author: 吴亮 | Hits:

[VHDL-FPGA-Verilog] Frequency-counter

Description: 基于FPGA的数字频率计：1. 测量1Hz～1GHz方波的频率，精度为十分位。 2. 档位自动调整，分为1Hz~999.9Hz,1KHz~999.9KHz,1MHz~999.9MHz三个档位。 3. 实现16位的除法器，进行频率的计算，并以ASIIC码输出测量的数据。 -FPGA-based digital frequency meter: 1. Measurement 1Hz ~ 1GHz square wave frequency, accuracy decile. (2) automatically adjusts the stalls, divided into 1Hz ~ 999.9Hz, 1KHz ~ 999.9KHz, 1MHz ~ 999.9MHz three stalls. 3 for 16-bit divider, the frequency calculations, and ASIIC code output measured data.
Platform: | Size: 133120 | Author: 曾 | Hits:

[VHDL-FPGA-Verilog] mc8051_design_1p5

Description: mc51单片机与fpga等精度频率计fpga的部分 mc51单片机与fpga等精度频率计fpga的部分 mc51单片机与fpga等精度频率计fpga的部分-mc51 microcontroller and fpga precision frequency meter fpga part mc51 microcontroller and fpga-precision frequency counter fpga' s part mc51 microcontroller and fpga precision frequency counter fpga' s part
Platform: | Size: 4962304 | Author: 林月乐 | Hits:

[Software Engineering] FPGA-based-frequency-counter

Description: 文章主要介绍了使用VHDL实现数字频率计的功能，其中包含了各部件的VHDL语言描述，仿真和大致硬件框图，对于初学EDA者大有帮助。-The article introduces the VHDL realization of the functionality of the digital frequency meter, which contains the hardware block diagram of the various components of the VHDL language description, simulation and approximate, and is a great help for beginners EDA.
Platform: | Size: 777216 | Author: 金刚 | Hits:

[VHDL-FPGA-Verilog] FREQUENCY-COUNTER

Description: Frequency counter, it uses the builtin display of FPGA spartan starter kit
Platform: | Size: 29696 | Author: zabic | Hits:

[Compress-Decompress algrithms] frequency-counter

Description: 这是用verilog写的配合DE2 FPGA开发板的10进制显示频率计的工程文件夹的压缩包，解压后可直接下载到DE2板上，其中频率输入端是系统自带27M时钟D13用于测试，如果想要应用于别的开发板，可以重新分配引脚。-DE2 FPGA development board with with verilog write with decimal display frequency meter project folder compression package, after decompression can be directly downloaded to the DE2 board, in which the frequency of the input of the system comes with 27M clock D13 used for testing If you want to apply to other development board can reassign pin.
Platform: | Size: 615424 | Author: 予烨 | Hits:

[Home Personal application] digital-frequency-counter

Description: 基于FPGA的数字频率计，verilog hdl编写-digital frequency counter ，using verilog hdl
Platform: | Size: 17408 | Author: 毋宁 | Hits:

[Other] Frequency

Description: 用VHDL语言实现频率计功能，加载到FPGA可以立即实现-With VHDL frequency counter function can be realized immediately loaded into the FPGA
Platform: | Size: 1024 | Author: 张中 | Hits:

[VHDL-FPGA-Verilog] FPGA-high-precision-frequency-meter

Description: 基于FPGA的高精度频率计设计实验 展示数字存储示波器基本工作原理。 展示硬件测频和测周的基本原理。 在现有综合实践平台上开发DSO硬件频率计模块的方案及流程。 结合数据采集、存储和触发模块的FPGA代码。 FPGA代码完善DSO的频率计模块，实现高精度测频和测周功能。-FPGA-based high-precision frequency meter design experiments       Demonstrate the basic working principle of digital storage oscilloscope.       Demonstrate the basic principles of frequency measurement and test hardware week. Developed on an existing platform integrated practice DSO hardware frequency counter module programs and processes. Combined with data collection, storage and trigger module FPGA code. FPGA code to improve DSO frequency meter module, high-precision frequency measurement and measurement capabilities week.
Platform: | Size: 14547968 | Author: liu | Hits:
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