Search - function vh

[VHDL-FPGA-Verilog] leon2-1[1].0.2a

Description: leon微处理器源代码，航空专用，功能强劲。包括详细说明-leon microprocessor source code, air flow, a strong function. Include a detailed description of
Platform: | Size: 919552 | Author: 王一 | Hits:

[VHDL-FPGA-Verilog] AD9851

Description: 用VHDL语言编写的DDS正弦函数发生器-Using VHDL language DDS sine function generator
Platform: | Size: 500736 | Author: cfsword | Hits:

[Other] ref-sdr-sdram-vhdl

Description: FPGA连接SDRAM的源程序，VHDL语言实现，功能基本完全。应用效果好。-FPGA connected SDRAM source, VHDL language, the basic function fully. Application effective.
Platform: | Size: 732160 | Author: young | Hits:

[Other] crc_pkg

Description: VHDL语言实现的CRC校验，函数形式，包括CRC4,CRC8,CRC16和CRC32-VHDL language to achieve the CRC checksum, function forms, including CRC4, CRC8, CRC16 and CRC32
Platform: | Size: 2048 | Author: 李浩 | Hits:

[VHDL-FPGA-Verilog] MotionEstimation_project_code

Description: Use verilog and VHDL to implement the Motion Estimation function, work as the hardware accelerator.
Platform: | Size: 315392 | Author: Ray Luo | Hits:

Description: 这是一个具有多功能的数字钟的VH语言文件，可能实现除最基本的时间功能外，还能整点报时及其它额外功能。-This is a multi-function digital clock VH language documents, possible exception of the most basic functions of time, but also the entire point of time and other additional features.
Platform: | Size: 5120 | Author: leonado | Hits:

[VHDL-FPGA-Verilog] LPT

Description: 实现开漏输出的并口，支持3.3V或5V，支持FPGA 的PS 配置功能。8位配置数据自动移位输出，输入时钟24MHz，产生1MHz配置时钟。8位CPU数据总线接口， 11位地址总线。支持IO 的置位清除功能。-The realization of open-drain output of the parallel port, support 3.3V or 5V, support for FPGA configuration of the PS function. 8-bit configuration data automatically shift output, input clock 24MHz, resulting 1MHz clock configuration. 8-bit CPU data bus interface, address bus 11. IO-bit support for the home clearance.
Platform: | Size: 2048 | Author: tianrongcai | Hits:

[VHDL-FPGA-Verilog] function_generator

Description: 采用VHDL语言写了一个函数发生器的程序。内含有各个模块，供大家参考，请多批评！-VHDL language used to write a function generator procedures. Contains various modules, for your reference, please criticize!
Platform: | Size: 12288 | Author: dqtyp | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: VHDL语言设计的秒表，实现计时功能，实现报时功能，并且通过硬件实验。-VHDL language design stopwatch, timer function of the realization, the realization of time functions, and through hardware experiments.
Platform: | Size: 1647616 | Author: 王蕊 | Hits:

[VHDL-FPGA-Verilog] generic_testbench

Description: VHDL中关于generic的用法，及其testbench，可以使用Modelsim仿真查看其功能-the usage of generic,a testbench file is given, we can use it to simulate the generic s function
Platform: | Size: 2048 | Author: xietianjiao | Hits:

[VHDL-FPGA-Verilog] LTC2624_TEST_OK

Description: 以简单的三角波来测试dac芯片LTC2426的功能是否正常.使用的开发板是Xilinx XC3S200AN,使用芯片的转化通道CHO,最后的输出结果为Vp-p大概为3.3V的三角波(Vp-p的大小由参考电压所决定)-A simple triangle wave dac chip to test whether the normal function of the LTC2426. The use of the development board is the Xilinx XC3S200AN, use the chips into channel CHO, the final output Vp-p for about 3.3V triangular wave (Vp-p size from determined by reference voltage)
Platform: | Size: 2199552 | Author: zhangjiansen | Hits:

[VHDL-FPGA-Verilog] 48led

Description: 此软件用的是QuartusII 5.1的环境编写的CPLD内的程序，CPLD用的是EPM7128，实现的功能是对计算机的ISA总线读写操作，计算机通过ISA总线，再通过CPLD，来控制LED的亮和灭-This software is used in the preparation of QuartusII 5.1 environment within the CPLD procedures, CPLD using EPM7128, the function of the realization of the ISA bus on the computer to read and write operation, the computer through the ISA bus, and then through the CPLD, to control the LED' s Liang and poverty
Platform: | Size: 201728 | Author: hujianhua | Hits:

[VHDL-FPGA-Verilog] PC8501

Description: 本程序为Verlog语言程序，采用QUARTUS6.0编写，程序实现的功能是控制AD2S80的转换和和数据总线上数据的读取-This program is Verlog language program, using QUARTUS6.0 preparation, program implementation function is to control the conversion and AD2S80 and data bus to read data
Platform: | Size: 1024 | Author: chendongkui | Hits:

[Mathimatics-Numerical algorithms] fir_filter

Description: 该数字滤波器通过结合matlab和vhdl来实现低通fir数字滤波器功能-The digital filter through a combination of matlab and vhdl to achieve low-pass digital filter function fir
Platform: | Size: 26624 | Author: caoge | Hits:

[Software Engineering] Fuzzy_PID_Control_of_Stepping_Motor

Description: 摘要:由于步进电动机调速系统具有非线性等特点,使得利用简单模糊控制与传统PID控制精度不高,因此文中提出利用模糊PID控制器实现对步进电动机调速系统进行控制的方法,并设计了模糊PID控制器。文中首先建立了步进电动机的数学模型,并根据数学模型推导了其传递函数然后介绍了模糊PID控制器结构,以及模糊控制规则的生成方法,并且对该控制方案进行数字仿真。仿真结果表明:该方法调节精度较高,动态响应快,无超调,有一定的可行性。 -Abstract: As the stepper motor drive system has nonlinear characteristics, which make use of simple fuzzy control with traditional PID control accuracy is not high, so this paper proposes to use fuzzy PID controller of the stepper motor drive system control, fuzzy PID controller was designed. At first the mathematical model of the stepping motor, and derived a mathematical model and its transfer function then describes the structure of fuzzy PID controller, and fuzzy control rule generation method, and digital simulation of the control program. Simulation results show that: the method to adjust the high accuracy, fast dynamic response, no overshoot, there is certainly feasible.
Platform: | Size: 138240 | Author: 孙文 | Hits:

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