Description: 本系统采用Visual C++语言编写,运用软件工程的思想, 采用面向对象分析、设计的方法学完成。通过建立系统的数据库,对象模型、动态模型、功能模型，设计界面窗口，算法结构，函数之间互相调用完成实现系统的功能。-the system using Visual C language, the use of software engineering, object-oriented analysis, the design methodology completed. Through the establishment of the system database, object model, the dynamic model, the functional model, user interface design, algorithm, Function call between achieving complete system. Platform: |
Size: 667164 |
Author:豪 |
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Description: Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download Platform: |
Size: 2015 |
Author:wyl |
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Description: bfm（总线功能模型）设计的基础教材，值得一看，需要lotus打开文档-BFM (bus functional model) designed on the basis materials, an eye-catcher, Lotus needs to open files Platform: |
Size: 52279 |
Author:wyl |
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Description: 具有中断处理功能模型机的设计与实现,计算机组成原理课程设计-interrupt handling is functional model for the design and implementation of computer architecture course design Platform: |
Size: 3500 |
Author:佳佳 |
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Description: 本系统采用Visual C++语言编写,运用软件工程的思想, 采用面向对象分析、设计的方法学完成。通过建立系统的数据库,对象模型、动态模型、功能模型，设计界面窗口，算法结构，函数之间互相调用完成实现系统的功能。-the system using Visual C language, the use of software engineering, object-oriented analysis, the design methodology completed. Through the establishment of the system database, object model, the dynamic model, the functional model, user interface design, algorithm, Function call between achieving complete system. Platform: |
Size: 666624 |
Author:豪 |
Hits:
Description: 本系统采用Visual C++语言编写,运用软件工程的思想, 采用面向对象分析、设计的方法学完成。通过建立系统的数据库,对象模型、动态模型、功能模型，设计界面窗口，算法结构，函数之间互相调用完成实现系统的功能。-the system using Visual C language, the use of software engineering, object-oriented analysis, the design methodology completed. Through the establishment of the system database, object model, the dynamic model, the functional model, user interface design, algorithm, Function call between achieving complete system. Platform: |
Size: 89088 |
Author:豪 |
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Description: 本系统采用Visual C++语言编写,运用软件工程的思想, 采用面向对象分析、设计的方法学完成。通过建立系统的数据库,对象模型、动态模型、功能模型，设计界面窗口，算法结构，函数之间互相调用完成实现系统的功能。-the system using Visual C language, the use of software engineering, object-oriented analysis, the design methodology completed. Through the establishment of the system database, object model, the dynamic model, the functional model, user interface design, algorithm, Function call between achieving complete system. Platform: |
Size: 275456 |
Author:豪 |
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Description: Gauss network model方法研究蛋白质运动模式的程序，可以用来分析蛋白质功能性运动-Gauss method network model protein movement patterns of procedures can be used to analyze protein functional movement Platform: |
Size: 1024 |
Author:苏计国 |
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Description: Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download Platform: |
Size: 2048 |
Author:wyl |
Hits:
Description: bfm（总线功能模型）设计的基础教材，值得一看，需要lotus打开文档-BFM (bus functional model) designed on the basis materials, an eye-catcher, Lotus needs to open files Platform: |
Size: 52224 |
Author:wyl |
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Description: 通过对银行储蓄管理系统的分析，进一步理解和掌握面向对象方法论，尤其是面向对象的三个模型：对象模型、动态模型、功能模型。-Bank savings through the analysis of management systems to further understand and grasp the object-oriented methodology, in particular, object-oriented three models: object model, dynamic model, functional model. Platform: |
Size: 193536 |
Author:常军伟 |
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Description: 多功能模型用控制器
使用PIC單晶片
用ASM語言撰寫-Multi-functional model with the use of PIC single-chip controller with ASM languages Platform: |
Size: 110592 |
Author:吳擬霸 |
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Description: 本方案为解决当前企业信息化建设中"信息孤岛"丛生、信息流不畅通、信息不能共享的瓶颈问题，强调首先搞好信息资源规划（Information Resource Planning,简称IRP），建立全企业的信息资源管理（Information Resource Management,简称IRM）基础标准，通过需求分析建立集成化信息系统的功能模型、数据模型和系统体系结构模型，然后再实施通信-计算机网络工程、数据库工程和应用软件工程。-The program for the solution to the current enterprise information construction in the information island problems, information flow is not smooth, the information can not be shared bottlenecks, emphasizing the first to do a good job of information resource planning (Information Resource Planning, referred to as IRP), the establishment of enterprise-wide Information Resources Management (Information Resource Management, referred to as IRM) based on standards, requirements analysis, through the establishment of integrated information system functional model, data model and system architecture model, and then the implementation of communication- computer network engineering, database engineering and application of software engineering. Platform: |
Size: 74752 |
Author:汪洋 |
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Description: 1. LDAP介绍 4
1.1. LDAP是什么 4
1.2. LDAP是电话簿 4
1.3. LDAP是不是数据库 4
2. LDAP的特点 5
2.1. LDAP的优势 5
2.1.1 跨平台 5
2.1.2 费用及维护 5
2.1.3 复制技术 5
2.1.4 允许使用ACI 5
2.2. LDAP存储什么数据 6
2.3. 什么时候该用LDAP存储数据 6
3. LDAP的基本模型 7
3.1 信息模型：描述LDAP的信息表示方式 7
3.2 命名模型：描述LDAP中的数据如何组织 7
3.3 功能模型：描述LDAP中的数据操作访问 7
3.4 安全模型：描述LDAP中的安全机制 8
3.4.1 身份认证 8
3.4.2 通讯安全 8
3.4.3 访问控制 8
..............
-1. LDAP Introduction 41.1. LDAP What is 41.2. LDAP is the Phonebook 41.3. LDAP database is 42. LDAP feature of 52.1. LDAP cross-platform advantages of 52.1.1 and 52.1.2 the cost of maintaining 52.1.3 replication technology 52.1.4 allowing the use of ACI 52.2. LDAP data storage What is 62.3. When the use of LDAP for storing data 63. LDAP basic model information model 73.1: Description of the information that way LDAP naming model 73.2: LDAP description how to organize the data in the functional model 73.3: Description LDAP data access operation 73.4 security model: Description of the security mechanism in LDAP Authentication 83.4.1 Security 83.4.2 Communications 83.4.3 Access Control 8 .............. Platform: |
Size: 12288 |
Author:阳光 |
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Description: 本程序包含：EEPROM的功能模型(eeprom.v)、读/写EEPROM的verilog HDL 行为模块（eeprom_wr.v）、信号产生模块（signal.v）和顶层模块(top.v) ，这样可以有一个完整的EEPROM的控制模块和测试文件，本文件通过测试。-This procedure includes: EEPROM of the functional model (eeprom.v), read/write EEPROM acts of verilog HDL modules (eeprom_wr.v), signal generator module (signal.v) and top-level module (top.v), this can have a EEPROM complete control module and test document, this document is to pass the test. Platform: |
Size: 109568 |
Author:周 |
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Description: 本文研究了SMBus
规范，介绍了典型的基于片上系统（SoC）设计的知识产权核（IP）实现，采用自顶向下
(Top-down)的集成电路设计方法完成了设计，并架构了基于总线功能模型(BFM)的验证平台
完成功能仿真，顺利完成了逻辑综合和时序仿真。FPGA 验证和投片后测试均表明设计具有
良好的性能。-This paper studies the SMBus specification, based on the introduction of the typical system-on-chip (SoC) intellectual property core design (IP) implementation, using top-down (Top-down) of the integrated circuit design methods achieve a design and architecture based on the total Line functional model (BFM) achieve functional verification platform for simulation, successfully completed a logic synthesis and timing simulation. FPGA silicon validation and post-tests show that the design has good performance. Platform: |
Size: 256000 |
Author:caorui |
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Description: 一个verilog源代码，可用ISE等实现，功能为I2C接口标准建模。-A verilog source code, can be used, such as the realization of ISE, the functional model for the I2C interface standard. Platform: |
Size: 306176 |
Author:PUDN_CHEN |
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Description: 宿舍管理系统(软件需求、软件的功能模型和信息模型)-Hostel Management System (software requirements, software, functional model and information model) Platform: |
Size: 193536 |
Author:wede123 |
Hits:
Description:
1） 8路数据采集功能
通过调节可变电阻实现0-5V的电压输出作为8路输入信号使用，每路信号用2位LED显示采集的结果。报警：任意一路超过某一门限（可自己设定）时，发出报警（声音+灯闪烁，并通过灯指示是哪一路报警），同时停止采集。
2） 计数功能
利用计数功能键，实现每按一次按键，LED显示加1，从0-99计数。
3） 秒表功能
只用一个键控制。按下一个按键后时钟启动，从零开始计时，计时间隔0.01秒，再按一次后停止。再按一次后清零。如此循环。
-3 function keys set up: When a function key is pressed after entering the corresponding functional model. Three features are:
1) 8-Channel Data Acquisition function by adjusting the variable resistor to achieve the 0-5V voltage output 8-channel input signal as the use of signals each with two LED display of the results collected. Alarm: any way above a certain threshold (which can be set), the issue of police (voice+ lights flicker, and through which light is the way the police instructions), at the same time to stop collecting. 2) counting function count function keys to use to achieve every time button, LED display plus 1, counting from 0-99. 3) with a stopwatch function keys control only. After pressing a button to start the clock, to start from scratch time, time interval 0.01 seconds, and then after a stop. And then once cleared. Such a cycle. Platform: |
Size: 105472 |
Author:孙国栋 |
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Description: J2流动理论加上破坏失效判据的程序，用于ABAQUS中的vumat程序，功能模拟加载到失效破坏的过程-J2 flow theory coupled with damage failure criteria of the program for the vumat ABAQUS program, functional simulation load to failure of the process of destruction Platform: |
Size: 3072 |
Author:华针 |
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Search - functional model