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[VHDL-FPGA-Verilog] I2S

Description: 这是一个I2S接口的VHDL实现源代码，I2S是一个通用的音频接口。-This is a I2S interface VHDL source code, I2S is a generic audio interface.
Platform: | Size: 1583104 | Author: 孙浩 | Hits:

[VHDL-FPGA-Verilog] generic_fifo

Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
Platform: | Size: 20480 | Author: daiowen | Hits:

[Software Engineering] FPGA_GFP

Description: 基于FPGA的GFP（通用成帧协议）封装数据成帧的实现。-FPGA-based GFP (Generic Framing Protocol) encapsulated data Framing realized.
Platform: | Size: 92160 | Author: ttttttt | Hits:

[File Format] designforvideobasedonSDRAM

Description: 在信息处理中，特别是实时视频图像处理中，通常都要对实现视频图像进行处理，而这首先必须设计大容量的存储器，同步动态随机存储器SDRAM虽然有价格低廉、容量大等优点，但因SDRAM的控制结构复杂，常用的方法是设计SDRAM通用控制器，这使得很多人不得不放弃使用SDRAM而使用价格昂贵的SRAM。为此，笔者在研究有关文献的基础上，根据具体情况提出一种独特的方法，实现了对SDRAM的控制，并通过利用FPGA控制数据存取的顺序来实现对数字视频图像的旋转，截取、平移等实时处理。-In information processing, especially real-time video image processing usually have to deal with video images, which must first be designed large-capacity memory, synchronous dynamic random access memory SDRAM Although there are low cost, large capacity, etc., but SDRAM control structure of the complex, commonly used method is to design generic SDRAM controller, which makes a lot of people had to abandon the use of SDRAM and the use of expensive SRAM. To this end, the authors examine the literature based on the specific situation in a unique way to realize the control of SDRAM, and control data through the use of FPGA to realize the order of access to digital video image rotation, interception, translation, such as real-time processing.
Platform: | Size: 137216 | Author: 赵明玺 | Hits:

[VHDL-FPGA-Verilog] SDR_SDRAM_controler_verilog

Description: 可以用的通用SDRAM控制器,可以用在FPGA上,是SDR类型的-Can use the generic SDRAM controller can be used in the FPGA, the SDR is the type of
Platform: | Size: 9216 | Author: 郑宏超 | Hits:

[VHDL-FPGA-Verilog] DUC

Description: 数字上变频DUC是与数字下变频ddc相对应的工作.目前实现方式主要有:专用芯片,通用DSP和FPGA实现三种.本程序即给出了XILINX公司的Digital Up Converter核心程序(IP CORE)以及响应的使用说明,对于从事雷达,无线通信的工程人员和研究者有很大用处.-DUC is a digital up-conversion and digital down conversion that corresponds to the work of ddc. Realize the current approach are: ASIC, DSP and FPGA generic realize three. This procedure is given that the company XILINX core Digital Up Converter program (IP CORE) and to respond to instructions, for radar, wireless communications, engineers and researchers have great usefulness.
Platform: | Size: 305152 | Author: 周严 | Hits:

[VHDL-FPGA-Verilog] FSCQ1565RP

Description: FSCQ1565RP J TAG驱动算法是MCU 以J TAG模式配置FPGA 的关 键。算法调用SVF 配置文件,解释其中的语法规范,生成严 格的TAP 总线时序,驱动MCU 的通用I/ O 管脚来完成对 FPGA 的配置。其中TAP 时序是算法设计和实现调试的一 个主要方面,时序关系[ 2 ]如图3 所示。-FSCQ1565RPJ TAG-driven algorithm is MCU to configure the FPGA model J TAG key. Algorithm called SVF profile, to explain the syntax specification to generate a strict TAP bus timing, driver MCU generic I/O pin to complete the configuration of the FPGA. TAP timing of which is the algorithm design and realization of a major aspect of debugging, timing relations [2] as shown in Figure 3.
Platform: | Size: 1143808 | Author: xujj | Hits:

[VHDL-FPGA-Verilog] cordic_generic

Description: 本人根据opencores.org上的cordic算法改写的可配置位宽的cordic算法，并且在原始的级联型的基础上编写的循环(iterative)型的cordic,可通过generic配置。带一个不可综合和可综合的testbench(for altera)。稍微改动可应用于xilinx fpga-a generic synthesizable cordic with 2 modes: cascade and iterative. based on opencores.org version, a synthesizable testbench please refer to www.opencores.org for documentation
Platform: | Size: 11264 | Author: Zhu | Hits:

[Other] fpga_memory_rev_1_0

Description: Various memories for Xilinx and Altera FPGA devices. Single-port and Dual-port versions with various numbers of read and write ports. Bundle also includes read-first and write-first varieties with sync and async clocks. All memory components are generic, permitting the word width and number of words to be specified easily.
Platform: | Size: 14336 | Author: Muhammed Hasan | Hits:

[VHDL-FPGA-Verilog] UserDefinedFunction

Description: It s a VHDL program. The program does a generic gray. Using a Cyclone II FPGA Board.
Platform: | Size: 242688 | Author: Ferdinando | Hits:

[VHDL-FPGA-Verilog] FPGA-usb-control

Description: USB 68013 通用固件 和配套上位机程序以及下位机FPGA程序verilog 可实现USB高速通信-USB 68013 generic PC firmware and supporting procedures and lower computer USB FPGA program can achieve high-speed communications
Platform: | Size: 8209408 | Author: | Hits:

[Software Engineering] aug09_2

Description: 基于FPGA的高性能离散小波变换设计，本设计在最高处理速度方面具有明显的优势。在此基础上，考虑到通用性的要求，本文还设计了一种小波种类可选、小波阶数可调的通用小波变换FPGA架构，该通用小波正、反变换系统的最高时钟频率分别为114.10 MHz、152.09 MHz。此结构具有通用性强的特点，可高性能实现多种小波变换。-Design high-performance FPGA-based discrete wavelet transform, this design has obvious advantages in terms of the highest processing speed. On this basis, taking into account the versatility of the request, also designed a wavelet type optional, wavelet order adjustable universal wavelet transform FPGA architecture, the generic wavelet is, the maximum clock frequency of the anti-transform system were 114.10 MHz, 152.09 MHz. This structure has the characteristics of versatility, high performance to achieve a variety of wavelet transform.
Platform: | Size: 1061888 | Author: kudding | Hits:

[VHDL-FPGA-Verilog] usb_device

Description: FPGA的一种实现usb设备通用方法，是nois的下的实现。-FPGA a usb device generic nois under implementation.
Platform: | Size: 3072 | Author: 林子 | Hits:

[VHDL-FPGA-Verilog] FSK

Description: 推荐一个FSK解调工程，用Actel FPGA 实现的比较通用，VHDL 源代码。-Recommended Actel FPGA implementation FSK demodulator engineering, more generic, VHDL realization.
Platform: | Size: 2861056 | Author: DAFEI | Hits:

[Other] sd

Description: SD卡fpga读写代码，比较通用，有需要的可以看下-SD card fpga read and write code more generic, there is need to look
Platform: | Size: 2048 | Author: 123 | Hits:

[Program doc] Software-Radio-Based-on-DSP

Description: 本文介绍了一种通用的软件无线电平台, 该平台以高性能DSP 为数据处理核心, 利用高速串行接口进行数据调度, 结 合外围的FPGA 和高速A/D、D/A, 可应用于多种制式的无线通信系统。-This paper describes a generic software radio platform, high-performance DSP core data processing, the use of high-speed serial interface for data scheduling, combined with external FPGA and high-speed A/D, D/A, can be applied to a variety of standard wireless communication system.
Platform: | Size: 277504 | Author: 曾维 | Hits:

[Linux-Unix] xillybus

Description: Xillybus driver for generic FPGA interface.
Platform: | Size: 9216 | Author: nyqpsk | Hits:

[VHDL-FPGA-Verilog] spi_verilog_master_slave_latest.tar

Description: 该项目从需要具有强大而简单的以VHDL编写的SPI接口核心开始，用于通用的FPGA到设备接口。 所产生的内核产生小而高效的电路，从非常慢的SPI时钟到超过50MHz的SPI时钟。-This project started the need to have robust yet simple SPI interface cores written in VHDL to use in generic FPGA-to-device interfacing. The resulting cores generate small and efficient circuits, that operate very slow SPI clocks up to over 50MHz SPI clocks.
Platform: | Size: 3072 | Author: asdtgg | Hits:

[VHDL-FPGA-Verilog] FPGA_EP4C

Description: Scematic and Verilog Examples for generic Cyclone iV board.
Platform: | Size: 9163776 | Author: thailera | Hits:

[Fax program] fifo

Description: Verilog HDL实现通用的FIFO的一个demo，可以参考这个程序根据自己的需求更改深度和宽度，以及标志位(Verilog HDL implements a demo of a generic FIFO that you can refer to to to change the depth and width, as well as the flag bits, depending on your needs)
Platform: | Size: 4649984 | Author: gankl | Hits:
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