Description: 算术逻辑部件的verilog代码,它能够实现半加器、全加器、比较、按位与、按位或、按位异或、加一、减一的操作-Arithmetic logic unit of the verilog code, it can achieve half adder, full adder, compare, bitwise and, bitwise or, bitwise xor, plus one, minus one operation Platform: |
Size: 169984 |
Author:李鹏飞 |
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Description: This a code programed in Verilog Language.
It is Full Adder code designed using Half Adder-This is a code programed in Verilog Language.
It is Full Adder code designed using Half Adder.. Platform: |
Size: 1024 |
Author:Faisal |
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Description: 此源代码是基于Verilog语言的多种方式实现的4 选 1 MUX、多种方式实现的4 选 2 MUX 、多种方式实现的1 位半加器 、多种方式实现的1 位全加器、种方式实现的 4 位全加器 、多种方式实现的输出 UDP 元件、两个时钟信号 、选择器 和各种仿真的源代码。-This source code is based on the Verilog language, multiple ways to achieve the 4 S 1 MUX, a variety of ways to achieve the 4 S 2 MUX, a variety of ways to achieve a half adder, a variety of ways to achieve a full adder, ways to achieve the 4-bit full adder, the output of a variety of ways to achieve UDP component, two clock signals, the selector and a variety of simulation source code. Platform: |
Size: 4096 |
Author:王柔毅 |
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Description: 用verilog在半加器的基础上实现了全加器,方法简单巧妙,对于FPGA入门学习很有帮助-In the half adder using verilog on the basis of a full adder, simple and clever, very helpful for the FPGA Starter Platform: |
Size: 273408 |
Author:孙超 |
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Description: These are first programs of my asic and fpgas lab.This folder contains simple half adder and its test bench using verilog language.Then it also contains 4 to 1 mux using two 2 to 1 muxes.Then its also has its test bench to check the code.These programs are really help ful for those who want to start the learning of verilog language. Platform: |
Size: 2048 |
Author:gul |
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Description: 这是一个最简单的四位的全加器设计,由两个半加器构成,采用的是VERILOG的算法级和门级描述的。-This is one of the easiest of the four full adder design, consists of two half-adder, the VERILOG algorithm-level and gate-level descriptions. Platform: |
Size: 168960 |
Author:邢金丹 |
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Description: 用Verilog语言实现的半加器功能,非常好的例程。-Verilog language implementation with half adder function, very good routine. Platform: |
Size: 233472 |
Author:毛超 |
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Description: FPGA的代码verilog语言编写,包括LED与按键验证,数据选择器,编码器,译码器半加器,全加器,适合初学者,已经在板子调试成功,板子是 睿智IV开发板。-FPGA code verilog language, including LED and key authentication, data selection, encoder, decoder and a half adder, full adder, suitable for beginners, it has been successful commissioning of the board, the board is wise IV development board. Platform: |
Size: 21079040 |
Author:ruanguopqing |
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Description: 用半加器搭建全加器 使用Verilog语言(Using a half adder to build a full adder, using the Verilog language) Platform: |
Size: 280576 |
Author:cadetblues
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Description: 大学生专业课的lab,用Verilog实现半加器(the necessary lab for college students to fulfill the function of half-adder) Platform: |
Size: 828416 |
Author:TwiNklE-BliNk |
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