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[Other resource] Debussy

Description: Debussy是NOVAS Software, Inc(思源科技)發展的HDL Debug & Analysis tool，這套軟體主要不是用來跑模擬或看波形，它最強大的功能是：能夠在HDL source code、schematic diagram、waveform、state bubble diagram之間，即時做trace，協助工程師debug。 可能您會覺的：只要有simulator如ModelSim就可以做debug了，我何必再學這套軟體呢? 其實Debussy v5.0以後的新版本，還提供了nLint -- check coding style & synthesizable，這蠻有用的，可以協助工程師了解如何寫好coding style，並養成習慣。 下圖所示為整個Debussy的原理架構，可歸納幾個結論： -Debussy is NOVAS Software, Inc. (source technology) development of the HDL Debug
Platform: | Size: 57293 | Author: frankyq | Hits:

[SCM] Debussy

Description: Debussy是NOVAS Software, Inc(思源科技)發展的HDL Debug & Analysis tool，這套軟體主要不是用來跑模擬或看波形，它最強大的功能是：能夠在HDL source code、schematic diagram、waveform、state bubble diagram之間，即時做trace，協助工程師debug。 可能您會覺的：只要有simulator如ModelSim就可以做debug了，我何必再學這套軟體呢? 其實Debussy v5.0以後的新版本，還提供了nLint -- check coding style & synthesizable，這蠻有用的，可以協助工程師了解如何寫好coding style，並養成習慣。 下圖所示為整個Debussy的原理架構，可歸納幾個結論： -Debussy is NOVAS Software, Inc. (source technology) development of the HDL Debug
Platform: | Size: 57344 | Author: frankyq | Hits:

[VHDL-FPGA-Verilog] LFSR

Description: 自动生成线形反馈移位寄存器的各种HDL源代码和原理图的工具-Automatic generation of linear feedback shift register of a variety of HDL source code and schematic tools
Platform: | Size: 162816 | Author: zx | Hits:

[VHDL-FPGA-Verilog] alu

Description: 设计带进位算术逻辑运算单元，根据74LS181功能表，用Verilog HDL硬件描述语言编程实现ALU181的算术逻辑运算功能，编辑实验原理图，在算术逻辑单元原理图上，将其扩展为带进位的算术逻辑运算单元，对其进行编译，并设计波形对其进行仿真验证，最后下载验证-Design into the digital arithmetic logic operation unit, in accordance with menu 74LS181 with Verilog HDL hardware description language programming ALU181 function arithmetic logic operations, editing Experimental schematic diagram, in the Arithmetic Logic Unit schematic diagram on its expansion into the spaces for arithmetic logic operation unit, its compiler, and the design of their simulation waveforms, and finally download the verification
Platform: | Size: 667648 | Author: 623902748 | Hits:

[Other] PLD-Design-Institut-for-10-minutes

Description: 10分钟学会PLD设计，分别采用VHDL、Verilog-HDL和原理图输入方式设计实验，并下载到PLD实验板进行实际运行。-PLD Design Institute for 10 minutes, respectively, the use of VHDL, Verilog-HDL and schematic design of the experimental input, and downloaded to the PLD to the actual operation of the experimental plate.
Platform: | Size: 870400 | Author: 宋大力 | Hits:

[VHDL-FPGA-Verilog] caiyang

Description: 种用FPGA 实现对高速A/ D 转换芯片的控制电路,系统以MAX125 为例,详细介绍了含有FIFO 存储器的A/ D 采样控制电路的设计方法,并给出了A/D 采样控制电路的V HDL 源程序和整个采样存储的顶层电路原理图.-Species with FPGA to achieve high-speed A/D conversion chip control circuit, the system as an example to MAX125 details FIFO memory contains A/D sampling control circuit design method, and gives the A/D sampling control circuit of the V HDL source code and the sample stored in the top-level circuit schematic.
Platform: | Size: 338944 | Author: 于银 | Hits:

[VHDL-FPGA-Verilog] EPM240_SCH_and_program

Description: EPM240 cpld 原理图+程序。 Verilog HDL语言。 程序有正弦波发生器，ADC0804直流采样和显示，汉字滚动，交通灯，键盘，显示程序，计数器等等。-Schematic diagram+ EPM240 cpld procedures. Sine wave generator procedures, ADC0804 DC sampling and showed that Chinese scroll, traffic lights, keyboard, display program, counters and so on.
Platform: | Size: 660480 | Author: student88 | Hits:

[VHDL-FPGA-Verilog] Lab01

Description: 快速熟悉ISE软件的使用，适合初学者，是一系列小操作流程的集合。-To become familiar with using Xilinx ISE to draw schematic representations of PLD circuits To become familiar with using Xilinx ISE to conduct graphical waveform simulations of PLD circuits To become familiar with using Xilinx ISE to write HDL representations of PLD circuits To become familiar with using Xilinx ISE to write HDL testbench simulations of PLD circuits To become familiar with downloading PLD circuits to the Nexys development board
Platform: | Size: 1250304 | Author: 飞飞三号 | Hits:

[VHDL-FPGA-Verilog] MulticlockCPU.tar

Description: verilog hdl实现多周期CPU，按照有限状态己设计，含源码、实验报告和详细vsd电路图-verilog hdl multi-cycle CPU, in accordance with the finite-state has been the design, including source code, test reports and detailed schematic vsd
Platform: | Size: 19317760 | Author: czl | Hits:

[VHDL-FPGA-Verilog] debussy

Description: Debussy 是NOVAS Software, Inc(思源科技)发展的HDL Debug & Analysis tool，这套软体主要不是用来跑模拟或看波形，它最强大的功能是：能够在HDL source code、schematic diagram、waveform、state bubble diagram之间，即时做trace，协助工程师debug。 本文主要是介绍Debussy的使用，以及如何在Modelsim环境下生成Debussy所需要的fsdb文件-user guide for using debussy. and how to import fsdb to debussy..
Platform: | Size: 286720 | Author: liangyao | Hits:

[VHDL-FPGA-Verilog] synth_fft

Description: fftprocessing can complete 256 pointsFFT.-Hardware Description Language(HDL)is an advanced electronic designmethod．After HDL was put into use，it has draw great attention and gained popularity．The design used Verilog HDL and Schematic for entry tools having good effect in the system design，Meanwhile，it adopted the core provided by Xilinx／nc. improving the design efficiency．The whole design which is implemented inXC2S600E device relied on ISE and advanced hierarchy design mind．Furthermore，it is simulated and verified．The frequency attains to 40.64MHz．this paper aims at demonstration the applying FPGA to FFT signal processing can complete 256 pointsFFT.
Platform: | Size: 56320 | Author: zzy | Hits:

[VHDL-FPGA-Verilog] verilog-HDL-learning

Description: 从零开始学verilog HDL ，包括Altera实验板原理图，xilinx实验板原理图和一些实验源程序-From scratch learn verilog HDL, including Altera experimental board schematic, xilinx test board schematics and source code of some experiments
Platform: | Size: 3766272 | Author: susu | Hits:

[VHDL-FPGA-Verilog] CPLD-Three-voting

Description: CPLD/FPGA 设计实例手册 用VHDL语言设计三人表决器 用原理图输入的方式设计三人表决器 用verilog-HDL语言设计三人表决器-CPLD/FPGA design example manual Three of the voting machine VHDL language Schematic design of a three-member voting Verilog-HDL language design three-member voting
Platform: | Size: 2754560 | Author: 叶子 | Hits:

[SCM] counter

Description: 计数器是数字电路系统中最基本的功能模块之一，设计时可以采用原理图或HDL语言完成。 下载验证时的计数时钟可选用连续或单脉冲，并用数码管显示计数值。 -The counter is one of the basic function module in the digital circuit system, can be used in the design of the schematic or HDL language completed. The download validation count clock choice of continuous or single pulse and count value with digital display.
Platform: | Size: 11264 | Author: | Hits:

[VHDL-FPGA-Verilog] Verilog_seg7

Description: Quartus的原理图和.v文件混合输入编程-The mixed input method of schematic File and Verilog HDL File for Quartus II
Platform: | Size: 3028992 | Author: 杨勇 | Hits:

[assembly language] EDA2012

Description: EDA实验代码步进电机控制以及HDL程序设计和原理图设计。-EDA experimental code stepper motor control, and HDL programming and schematic design.
Platform: | Size: 3793920 | Author: joeeer | Hits:

[VHDL-FPGA-Verilog] second

Description: 利用Verilog HDL语言进行数字系统设计实现秒表的设计，涵盖原理图设计、文本设计以及进行波形仿真，并有对应的报告。报告中还包括BCD/7段译码集成电路74LS47仿真实验、单管分压式稳定工作点偏置电路仿真实验和8路智力竞赛抢答器电路设计-Use Verilog HDL language design and implementation of digital systems design stopwatch, covering schematic design, text, design, and simulation waveform, and there is a corresponding report. The report also includes a BCD/7 segment decoder IC 74LS47 simulation, single-tube type stable operating point voltage divider bias circuit simulation and 8 quiz Responder circuit design
Platform: | Size: 465920 | Author: 文闯 | Hits:

[File Format] hardwired

Description: 掌握硬连线控制器的设计方法。掌握硬连线控制器的Verilog HDL描述方法。了解QUARTUS II硬件描述语言和原理图混合输入设计的过程。 -Master the design method of hard wired controller. Grasp the hard wired controller Verilog HDL description method. To understand the process of QUARTUS II hardware description language and schematic design of hybrid input.
Platform: | Size: 4506624 | Author: 刘祖媛 | Hits:

[Other] Design_Implementation_of_DDR2___DDR3_Interfaces.r

Description: Extensive background in PCB development, Library Management, EDA Software support and value added Process Improvement. Expert using the Cadence Allegro PCB Tool Suite with Cadence Allegro DE HDL and OrCAD schematic capture tools.
Platform: | Size: 2747392 | Author: Alexander | Hits:

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