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Description: HDLC接口的实现，用VHDL写的，带有文档！-HDLC interface, written using VHDL, with documentation!
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Size: 177152 |
Author: 刘志刚 |
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Description: 利用verilog硬件描述语言编写的8为并行输入的常crc校验模块。hdlc子模块-Using Verilog hardware description language for the parallel importation of 8 regular CRC checksum module. HDLC sub-modules
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Size: 1024 |
Author: 张纪强 |
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Description: 采用Altera公司的FPGA芯片，在MAX+plus II软件平台上实现多路HDLC电路-Using Altera s FPGA chips, in MAX+ Plus II software platform to achieve multi-channel HDLC circuit
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Size: 62464 |
Author: yangj2 |
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Description: 用VHDL实现从以太网到并行数据以及从并行数据到以太网的HDLC成帧解帧.附详细代码说明,方便阅读.可方面移植到Altera及Xilinx等厂家芯片,是做基于FPGA的以太网设计的好资料-Achieved using VHDL and parallel data from the Ethernet to parallel data from the HDLC framing solution to Ethernet frames. Attached detailed code instructions, easy to read. Can be ported to Altera and Xilinx areas such as chip manufacturers are doing to FPGA-based very good information network design
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Size: 11264 |
Author: 卓福洲 |
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Description: 基于FPGA的hdlc协议控制器的实现，用vhdl语言编写。-FPGA-based implementation of hdlc protocol controller, using vhdl language.
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Size: 6144 |
Author: zizi |
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