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[VHDL-FPGA-Verilog] pci_vhdl

Description: PCI的VHDL源码希望对大家有用！-PCI VHDL source hope useful for all!
Platform: | Size: 27648 | Author: 林建加 | Hits:

[Other] VHDLcourse

Description: 好书推荐之VHDL经典实用教程中文版（相当不错的教材）@arthurday-the recommended books VHDL Practical Guide to Classical Chinese version (quite materials) @ arthurday
Platform: | Size: 16908288 | Author: xingqiba | Hits:

[ARM-PowerPC-ColdFire-MIPS] hdlc.tar

Description: HDLC接口的实现，用VHDL写的，带有文档！-HDLC interface, written using VHDL, with documentation!
Platform: | Size: 177152 | Author: 刘志刚 | Hits:

[VHDL-FPGA-Verilog] hdlc

Description: HDLC通信模块发送接收模块VHDL源码-HDLC communication module to send receiver module VHDL source code
Platform: | Size: 3072 | Author: ditto | Hits:

[ARM-PowerPC-ColdFire-MIPS] crc16_8bit.v

Description: 利用verilog硬件描述语言编写的8为并行输入的常crc校验模块。hdlc子模块-Using Verilog hardware description language for the parallel importation of 8 regular CRC checksum module. HDLC sub-modules
Platform: | Size: 1024 | Author: 张纪强 | Hits:

[VHDL-FPGA-Verilog] hdlc_vhdl

Description: This a VHDL implementation of an HDLC controller
Platform: | Size: 180224 | Author: | Hits:

[Embeded-SCM Develop] HDLC

Description: 在通讯领域中使用相当广泛的HDLC，这是一个参考设计，希望对一些人有用。-In the area of communications used in a wide range of HDLC, which is a reference design with the hope of useful for some people.
Platform: | Size: 2253824 | Author: jasonchen | Hits:

[VHDL-FPGA-Verilog] FPGAforDLC

Description: 采用Altera公司的FPGA芯片，在MAX+plus II软件平台上实现多路HDLC电路-Using Altera s FPGA chips, in MAX+ Plus II software platform to achieve multi-channel HDLC circuit
Platform: | Size: 62464 | Author: yangj2 | Hits:

[Embeded-SCM Develop] HDLC

Description: hdlc帧接收器 包含文件： 设计代码 测试代码 综合脚步 说明文档-HDLC frame receiver include file: design code test code Comprehensive documentation footsteps
Platform: | Size: 447488 | Author: wangjie | Hits:

[Other] hdlc_latest.tar

Description: HDLC在通讯设备中占有重要地位，本文件提供了完整正确的HDLC的硬件逻辑设计！对设计和学习都具有参考价值-HDLC in the communications equipment plays an important role, this document is to provide a complete hardware HDLC correct logic design! Design and learning have a reference value
Platform: | Size: 177152 | Author: 欧阳秋 | Hits:

[Embeded-SCM Develop] hdlc-code

Description: 用硬件描述语言实现HDLC通道的功能,取代HDLC专用芯片-Hardware description language used to achieve the functions of HDLC channel to replace the HDLC ASIC
Platform: | Size: 11264 | Author: zhanghf | Hits:

[Embeded-SCM Develop] hdlc

Description: hdlc 总线的vhdl 的样例代码。包含代码和说明文档。-hdlc-bus vhdl sample code. Contains code and documentation.
Platform: | Size: 205824 | Author: rensijun | Hits:

[Com Port] insert_zero

Description: 可以实现HDLC帧结构中的添零功能，使得信息部分不会和HDLC帧头部分混淆。-can insert zero to the hdlc frame,
Platform: | Size: 1024 | Author: 王瑜 | Hits:

[Communication-Mobile] del

Description: 他可以完成HDLC帧的删零功能，使得收端能够正确的恢复出HDLC中携带的信息-it can delete the zero from the HDLC frame ,make the information correct.
Platform: | Size: 1024 | Author: 王瑜 | Hits:

[VHDL-FPGA-Verilog] trunk-hdlc

Description: 高级链路层协议的实现，vhdl，fpga-- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern is assumed only after the end of a frame which is signaled by an abort signal - Zero insertion - Abort pattern generation and checking - Address insertion and detection by software - CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used) - FIFO buffers and synchronization (External) - Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted) - Q.921, LAPB and LAPD compliant. - For complete specifications refer to spec document
Platform: | Size: 188416 | Author: | Hits:

[VHDL-FPGA-Verilog] hdlc

Description: 基于FPGA的HDLC协议控制器，能完成插零，删除0操作。-HDLC controller base on FPGA
Platform: | Size: 197632 | Author: | Hits:

[VHDL-FPGA-Verilog] hdlc

Description: HDLC接口协议的FPGA实现使用verilog-design of HDLC
Platform: | Size: 3697664 | Author: hanjinchao | Hits:

[VHDL-FPGA-Verilog] hdlc

Description: HDLC协议的VHDL源码。接收和发送模块，以及所用FIFO的IP核（Xilinx公司）。-The code of HDLC protocol.Receive and transmit module is contained.
Platform: | Size: 10240 | Author: wei | Hits:

[VHDL-FPGA-Verilog] FPGA-HDLC-design

Description: 基于FPGA的HDLC协议控制器的设计。FPGA-based HDLC protocol controller design. Pdf-FPGA-based HDLC protocol controller design. Pdf
Platform: | Size: 1596416 | Author: iriu | Hits:

[VHDL-FPGA-Verilog] HDLC

Description: verilog HDL语言编写的HDLC协议的IP核，包括通讯控制及CRC。-written in verilog HDL HDLC protocol IP core, including communications control and CRC.
Platform: | Size: 69632 | Author: 王强 | Hits:
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