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[VHDL-FPGA-Verilog] Exp6-VGA

Description: 通过UART从PC主机读取图片数据，并完成图片在VGA显示器上的显示-through UART from the host PC to read image data, and complete picture of the VGA display on the show
Platform: | Size: 681984 | Author: 萧飒 | Hits:

[Embeded-SCM Develop] vspi_VHDL

Description: FPGA/CPLD VHDL语言实现SPI，拥有两种模式，FPGA/CPLD即可工作在主机模式，又可工作在从机模式 -FPGA/CPLD VHDL language SPI, have the two models, FPGA/CPLD can work in host mode, but also work in slave mode
Platform: | Size: 248832 | Author: 张焱 | Hits:

[VHDL-FPGA-Verilog] vhdl3

Description: 时序电路——抢答器，K1、K2、K3、K4各控制一个按钮，DJ代表主持人，在抢答开始前，DJ先按一下按钮，然后在开始比赛，K1—K4中任意按下按钮后，其他钮按下均无效，重新比赛时，DJ需要再按一下按钮。抢答结果用LED显示。-Sequential Circuits- Answer devices, K1, K2, K3, K4 the control of a button, DJ on behalf of the host before the start of the Answer, DJ press the button, and then at the beginning of competition, K1-K4 in the arbitrary press the button and press the other buttons are invalid, re-match, DJ need to then click the button. Answer the result of using LED display.
Platform: | Size: 97280 | Author: wang | Hits:

[VHDL-FPGA-Verilog] VHDLProgram36MHz

Description: 可以受上位机控制的通过fpga的视频信号发生器程序，可控制屏幕上产生各种运动图像-Can be controlled by the host computer through the FPGA of the video signal generator procedures, can control the screen images have a wide variety of sports
Platform: | Size: 4202496 | Author: xianchunwwang | Hits:

[VHDL-FPGA-Verilog] ps2core

Description: 一个ps2键盘鼠标的Host Controller。实现接收键盘及鼠标发送的数据的要求。基于FPGA。-A ps2 keyboard and mouse of the Host Controller. Realize receive keyboard and mouse to send data requirements. Based on the FPGA.
Platform: | Size: 20480 | Author: 颜新卉 | Hits:

[3G develop] usbhostslave

Description:
Platform: | Size: 701440 | Author: xiaojian | Hits:

[DSP program] pcitohpi16

Description: 主机通过pci9054与c6713的hpi接口读取dsp的所有内外存，哎，为什么一定要传5个呢？-PCI9054 host through the HPI interface with the c6713 to read all the internal and external dsp survival, hey, why must it Chuan-5?
Platform: | Size: 2048 | Author: 丁科 | Hits:

[SCM] ps2_rs232

Description: 本实验实现PS/2接口与RS-232接口的数据传输， PS/2键盘上按下按键，可以通过RS-232自动传送到主机的串口调试终端上（sscom32.exe）； 并在数据接收区显示接收到的字符。 串口调试终端的设置：波特率115200，一个停止位，无校验位。 -Realize this experiment, PS/2 interface with RS-232 data interface, PS/2 keyboard to press the button, through RS-232 automatic transmission to the host serial debug terminal (sscom32.exe) and data receiving display received characters. Serial debug terminal settings: 115200 baud rate, one stop bit, no parity bit.
Platform: | Size: 196608 | Author: yuan | Hits:

[VHDL-FPGA-Verilog] RS232

Description: 本实验实现PS/2接口与RS-232接口的数据传输， PS/2键盘上按下按键，可以通过RS-232自动传送到主机的串口调试终端上（sscom32.exe）； 并在数据接收区显示接收到的字符。 串口调试终端的设置：波特率115200，一个停止位，无校验位。-Realize this experiment, PS/2 interface with RS-232 data interface, PS/2 keyboard to press the button, through RS-232 automatic transmission to the host serial debug terminal (sscom32.exe) and data receiving display received characters. Serial debug terminal settings: 115200 baud rate, one stop bit, no parity bit.
Platform: | Size: 730112 | Author: 李华 | Hits:

[VHDL-FPGA-Verilog] UART_SUCCESS

Description: 实现FPGA和上位机的串口通信，里面由波特率发生器，移位寄存器，计数器，detecter,switch,switch_bus等功能块综合而成。-FPGA implementation and the host computer' s serial communication, which by the baud rate generator, shift register, counters, detecter, switch, switch_bus such as function blocks integrated together.
Platform: | Size: 1855488 | Author: zhn | Hits:

[VHDL-FPGA-Verilog] qiangdaqi

Description: 用verilog编写的抢答器，当主持人宣布“开始比赛”，系统初始化，选手进入“抢答状态”。当某一选手首先按下抢答开关时，相应的指示灯亮，此时抢答器不再接受其他输入信号。电路具有累计分控制（分别用４个４位选手的积分——十六进制数），由主持人控制“加分”。“加分”加分完毕，开始下一轮抢答。电路还可以设有回答问题时间控制。 -Answer using Verilog prepared, and when the host announced the " start game" , the system initialization, players enter the " Answer status." When a player first of all, press the Answer the switch, the corresponding indicator light, when the Answer Explorer no longer accept other input signals. Circuit with a total of sub-control (separately with four players four points- hexadecimal number), by the host control " points." " Add points" add hours after beginning the next round of Answer. Circuit can also be equipped with time control to answer questions.
Platform: | Size: 1103872 | Author: 叶 | Hits:

[USB develop] usb

Description: USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.-USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.
Platform: | Size: 6144 | Author: polito | Hits:

[Communication-Mobile] wb_lpc_latest.tar

Description: Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided. None of this has been tested (yet) with a third-party LPC Peripheral or Host.
Platform: | Size: 410624 | Author: Arun | Hits:

[Com Port] FPGArs232

Description: FPGA中实现rs232串口通信程序，上位机和FPGA互发数据-FPGA to achieve rs232 serial communication procedures, each host computer and FPGA-fat data
Platform: | Size: 100352 | Author: wg | Hits:

[VHDL-FPGA-Verilog] Exp6-VGA

Description: Create-SOPC1000X 嵌入式开发平台、用于 FGPA的 JTAG 下载电缆、VGA显示器、 串口数据线、PC主机。 -Create-SOPC1000X embedded development platform for FGPA the JTAG download cable, VGA display, serial data cable, PC host.
Platform: | Size: 662528 | Author: yangcheng | Hits:

[SCM] qiangdaqi

Description: 　 (1) 抢答器线路测试功能 　　为了保证比赛的正常进行，比赛前需要调试线路能否正常工作。 　　 (2) 第一抢答信号的鉴别和锁存功能 　　可以判断谁最先抢到回答的资格，其相应的绿灯表示抢答成功，并具有锁存功能，一直到下一题开始。 　　 (3) 犯规警示功能 　　可以判断出参赛者有没有在主持人读题的期间按下抢答器，有则相应的红灯亮，同时取消其本轮抢答资格。 　　 (4) 计时功能 　　可以预置时间，可以进行倒计时并且将时间显示出来。 　　 (5) 计分功能 可以实现加分，并且显示出来 -(1) Answer line testing device in order to ensure the normal game, the need to debug line before the game can work properly. (2) Answer the first to identify and latch signals to determine who can be the first to get the qualifications to answer, and its corresponding Answer green that success and with latch function, until the beginning of the next title. (3) foul warning function can be judged contestants have read in the host during the press Answer questions, and there is a corresponding red light, at the same time cancel the current round of qualifications Answer. (4) The time functions can be preset time, the countdown can be displayed and the time. (5) scoring function points can be achieved and displayed.
Platform: | Size: 956416 | Author: 孙国栋 | Hits:

[Communication-Mobile] sdcard_mass_storage_controller

Description: A host controlled ot control sd cards
Platform: | Size: 2270208 | Author: Anand Krishna | Hits:

[VHDL-FPGA-Verilog] 232

Description: 实现PS/2接口与RS-232接口的数据传输， 可以通过RS-232自动传送到主机的串口调试终端上并在数据接收区显示接收到的字符。-The realization of PS/2 port RS-232 interface with data transfer, RS-232 can be automatically sent to the host serial debug terminal and reception area in the data display received characters.
Platform: | Size: 15360 | Author: 包宰 | Hits:

[SCSI-ASPI] scsi

Description: 传统存储阵列接口，用于构建scsi host adapter-traditional storge matrix interface，used for scsi host adapter design
Platform: | Size: 4096 | Author: 刘月 | Hits:

[Books] usb

Description: 在高速的数据采集或传输中，目前使用较多的都是采用USB 2．0接口控制器和FPGA或DSP实现的，本设计在USB 2．0接口芯片CY7C68013的Slave FIFO模式下，利用FPGA作为外部主控制器实现对FX2 USB内部的FIFO进行控制，以实现数据的高速传输。该模块可普遍适用于基于USB 2．0接口的高速数据传输或采集中。-In the high-speed data acquisition or transmission, the currently used are based on more USB 2.0 interface controller and the FPGA or DSP implementation, the design USB 2.0 interface chip CY7C68013 of the Slave FIFO mode, the use of FPGA as a the external FX2 USB host controller to realize the internal FIFO control, in order to achieve high-speed data transmission. The module can be generally applied based on high-speed USB 2.0 interface, transfer or acquisition of data.
Platform: | Size: 894976 | Author: jiang_jennifer | Hits:
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