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[VHDL-FPGA-Verilog] bbb

Description: AVS运动补偿电路的VLSI设计与实现 提出了一种基于AVS标准的高效的运动补偿电路硬件结构，该设计采用了8 X 8块级流 水线操作，运动矢量归一化处理和插值滤波器组保证了流水线的高效运行以及硬件资源的最优 利用。采用Verilog语言完成了VLSI设计，并通过EDA软件给出仿真和综合结果。-AVS motion compensation circuit of VLSI Design and Implementation of a standard based on the AVS motion compensation circuit efficient hardware structure, the design used 8 X 8 block-level pipelining, the normalized motion vector processing and interpolation filter bank guarantee efficient operation of the pipeline, as well as the optimal use of hardware resources. Using Verilog language completed VLSI design and EDA software through simulation and synthesis results.
Platform: | Size: 216064 | Author: sss | Hits:

[Other] hbf

Description: 在软件无线电中半带滤波器的设计与实现，半带滤波器实现的是2的幂次的抽取或插值。 -In software radio half-band filter design and realization of half-band filter is the realization of 2-power extraction or interpolation.
Platform: | Size: 246784 | Author: 岑楠 | Hits:

[VHDL-FPGA-Verilog] cic

Description: verilog码写的CIC滤波器的程序，包括4倍抽取CIC滤波器和内插的CIC滤波器两个-Verilog code written by CIC filter procedures, including 4 times the extraction CIC filter and the CIC interpolation filter two
Platform: | Size: 22528 | Author: 桃子 | Hits:

[SCM] cic1s2

Description: 单级CIC2倍内插滤波器，用verilogHDL实现-CIC2 times the single-stage interpolation filter, used to achieve verilogHDL
Platform: | Size: 498688 | Author: Carl | Hits:

[VHDL-FPGA-Verilog] hbf

Description: 半带插值滤波器设计、综合、仿真和硬件测试-Half-band interpolation filter design, synthesis, simulation and hardware test
Platform: | Size: 18432 | Author: pll | Hits:

[VHDL-FPGA-Verilog] baseband_verilog

Description: verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器-verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum modules, polarity transform and interpolation modules, forming filter
Platform: | Size: 26624 | Author: 刘新 | Hits:

[VHDL-FPGA-Verilog] cic_intp_64_four

Description: 4阶CIC内插滤波器，内插系数64，Verilog版本，数字下变频-4-order interpolating CIC filter interpolation factor of 64, Verilog version of the digital down-conversion
Platform: | Size: 1024 | Author: 王刚 | Hits:

[VHDL-FPGA-Verilog] interpolation-filer-rtl

Description: synthesizable verilog rtl implemetation of interpolation filter, for both asic and fpga. 64x interpolation. interp_filter.v interp_first.v interp_second.v interp_third.v upsample.v
Platform: | Size: 3072 | Author: swordever | Hits:

[VHDL-FPGA-Verilog] interp_24_cic

Description: 基于fpga的插值CIC滤波器设计,采用verilog编写，24倍插值,仿真通过-Fpga-based interpolation CIC filter design using verilog write, 24x interpolation, through simulation
Platform: | Size: 2336768 | Author: zengdeqian | Hits:

[VHDL-FPGA-Verilog] cic_cz

Description: 在altera平台用verilog硬件描述语言实现cic插值滤波，在modelsim软件中仿真通过，包含完整的工程代码，可以直接下载到FPGA中运行-In the Altera platform using Verilog hardware description language CIC interpolation filter, through the simulation in Modelsim software, including the complete project code, can be directly downloaded to the FPGA operation
Platform: | Size: 1086464 | Author: 汪少锋 | Hits:

[VHDL-FPGA-Verilog] interpolate4

Description: 调制信号后4倍内插的verilog代码，用于基带成型滤波器输入数据-4 times after modulation signal interpolation verilog code, used to baseband shaping filter input data
Platform: | Size: 1024 | Author: 右下角 | Hits:

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