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[Linux-Unix] udpgen.c

Description: IP流量发生器，用于产生UDP报文，该程序用于模拟你需要的IP流量。可运行于Linux-IP flow generator, used to produce UDP packet, the procedure you need to simulate the IP flow. Can be run on Linux
Platform: | Size: 1024 | Author: Rex Yan | Hits:

[Other] HowtosimulateIPCore

Description: IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则 asyn_fifo.veo 给出了例化该核方式（或者在 Edit－>Language Template->COREGEN 中找到 verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库 的模块，仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit-
Platform: | Size: 359424 | Author: 任学 | Hits:

[VHDL-FPGA-Verilog] MATLAB_sg_IP

Description: 使用MATLAB为System Generator for DSP创建IP-The use of MATLAB for System Generator for DSP to create IP
Platform: | Size: 39936 | Author: lxd | Hits:

[matlab] MATLAB-sg-DSP-IP

Description: 使用MATLAB为System Generator for DSP创建IP-The use of MATLAB for System Generator for DSP to create IP
Platform: | Size: 39936 | Author: lxd | Hits:

[Windows Develop] Ip_Generator

Description: vb6 ip generator(the source)
Platform: | Size: 3072 | Author: gage | Hits:

[Internet-Network] ipgenerator2

Description: header file of the ip generator-header file of the ip generator
Platform: | Size: 1024 | Author: Amer82 | Hits:

[Internet-Network] logcsourceip

Description: header file of ip generator-header file of ip generator
Platform: | Size: 2048 | Author: Amer82 | Hits:

[Windows Develop] ip_generator.rb

Description: ip generator for random ip addresses, used to generate a list of a lot of ip addresses
Platform: | Size: 1024 | Author: dejan | Hits:

[VHDL-FPGA-Verilog] uart16550_latest[1].tar

Description: 开源UART IP核16550，该IP核兼容16550 UART，具有Modem功能，完全可编程的串行接口具有可设置的字符长度、奇偶校验、停止位以及波特率生成器。-Open-source UART IP core 16550, the IP core is compatible with 16550 UART, with Modem function, fully programmable serial interface can be set up with a character length, parity, stop bits and baud rate generator.
Platform: | Size: 1559552 | Author: lisa1027 | Hits:

[Books] Block_Memory_Generator_v3.3

Description: Xilinx IP core 生成手册-Block_Memory_Generator
Platform: | Size: 1935360 | Author: wang pu | Hits:

[TCP/IP stack] vbfrance_GENERATEUR-TRAME-IP-UDP___Page

Description: source code for a frame generator UDP/IP
Platform: | Size: 48128 | Author: sloumanaw | Hits:

[VHDL-FPGA-Verilog] ISE_lab17

Description: 本实验使用 XILINX 提供的IP 核，并例化该IP 核来实现正弦信号发生器的功能。由于 ISE 中有DDS（Direct Digital Synthesizer 5.0）IP 核，因此只需要编写一个顶层文件来调用 Core Generator 生成的IP 即可。-This study provides the IP core using the XILINX, and cases of the IP core to achieve the sinusoidal signal generator functions. ISE in the DDS (Direct Digital Synthesizer 5.0) IP core, so only need to write a top-level file to call the IP Core Generator can generate.
Platform: | Size: 4096 | Author: | Hits:

[VHDL-FPGA-Verilog] Whats-New-in-CORE-Generator-and-IP

Description: ise13.1中有什么新的ip核和资源，希望用ise的朋友能好好看看。-ise13.1 What' s new in the ip nuclear and resources in the hope that friends can have a good look at ise.
Platform: | Size: 8192 | Author: 飞飞 | Hits:

[e-language] IPR-Generator

Description: 通过纯真IP数据库生成“代理猎手”所支持的IP段IPR文件-" Agent Hunter generated by pure IP database support IP IPR file
Platform: | Size: 4303872 | Author: 林志豪 | Hits:

[Internet-Network] logcsourceip

Description: header file of ip generator-header file of ip generator
Platform: | Size: 2048 | Author: yearin | Hits:

[Game Program] ipgenerator2

Description: header file of the ip generator-header file of the ip generator
Platform: | Size: 1024 | Author: fitedfr | Hits:

[Game Program] logcsourceip

Description: header file of ip generator-header file of ip generator
Platform: | Size: 2048 | Author: ywisewit | Hits:

[uCOS] ar32713_xlt202a_v5_gmii

Description: Code ip generator for fpga altera
Platform: | Size: 3072 | Author: gio | Hits:

[VHDL-FPGA-Verilog] CRC-generator

Description: 提出了一种32位并行和高度流水线的循环冗余码（CRC）发生器。 该设计可以处理5个不同的通道，每个输入速率为2Gbps（总输出吞吐量为5x4Gbps）。 生成的CRC与32位以太网标准兼容。 该电路已经在0.35Micron标准CMOS工艺中使用标准单元实现，其使用Galois Fields的特性，并且被认为是“自由的”IP。-A 32-bit parallel and highly pipelined Cyclic Redundancy Code (CRC) generator is presented. The design can handle 5 different channels at an input rate of 2Gbps each (the total output throughput is 5x4Gbps.) The generated CRCs are compatible with the 32-bit Ethernet standards. The circuit has been implemented with standard cells in a 0.35Micron standard CMOS process using the properties of Galois Fields and has been conceived as a free IP.
Platform: | Size: 449536 | Author: asdtgg | Hits:

[VHDL-FPGA-Verilog] Xilinx

Description: 2020 XILINX Vivado ISE IP License最全最可靠License获取方式。 LDPC, CPRI, Turbo, Polar, JESD204B/C HDMI1.4/2.0, MIPI CSI-2, MIPI DSI AXI CAN AXI USB2.0 SD Card Host Reed-Solomon Decoder/Encoder 10G Enthernet MAC 25G Enthernet MAC 40G Enthernet MAC 50G Enthernet MAC 100G Enthernet MAC RS Encoder/Decoder Display Port/ DP Video Test Pattern Generator RapidIO tri mode ethernet mac(LDPC, CPRI, Turbo, Polar, JESD204B/C HDMI1.4/2.0, MIPI CSI-2, MIPI DSI AXI CAN AXI USB2.0 SD Card Host Reed-Solomon Decoder/Encoder 10G Enthernet MAC 25G Enthernet MAC 40G Enthernet MAC 50G Enthernet MAC 100G Enthernet MAC RS Encoder/Decoder Display Port/ DP Video Test Pattern Generator RapidIO tri mode ethernet mac)
Platform: | Size: 1024 | Author: liyan2020 | Hits:
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