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Description: MaxplusII编写的简易cpu，可实现简单加减法等操作-MaxplusII summary prepared by the cpu can realize simple addition and subtraction, etc
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Size: 513418 |
Author: godtroop |
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Description: ＦＰＧＡ数字钟的设计，用VHDL语言编程，max+plus仿真，可在实际电路中验证-FPGA design, VHDL programming, max plus simulation, in the actual circuit verification
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Size: 269312 |
Author: 王越 |
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Description: MaxplusII编写的简易cpu，可实现简单加减法等操作-MaxplusII summary prepared by the cpu can realize simple addition and subtraction, etc
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Size: 513024 |
Author: godtroop |
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Description: 16位cpu设计VHDL源码，其中包括alu，clock，memory等部分的设计-16 cpu design VHDL source code, including alu, clock, memory and other parts of the design
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Size: 1089536 |
Author: 孙冰 |
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Description: 实现简单CPU功能的源码，可以实现加减乘除和移位功能，VHDL代码，程序运行在MAX PULS和Quartua上。-The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. The Altera’s Maxplus Ⅱ EDA tool is recommended and provided for simulation.
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Size: 4490240 |
Author: 灿烂六月 |
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Description: 在maxplus上实现了一个5级流水线的mips cpu，含cache-In maxplus to achieve a 5-stage pipeline of the mips cpu, with cache
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Size: 449536 |
Author: tong tong |
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Description: 本设计实现了一个具有标准的32位5级流水线架构的MIPS指令兼容CPU系统。具备常用的五十余条指令，解决了大部分数据相关，结构相关，乘除法的流水化处理等问题，并实现了可屏蔽的中断网络。-This design implements a standard 32-bit 5-stage pipeline architecture of MIPS instruction compatible CPU system. Instructions with more than 50 commonly used to solve most of the data related to the structure related to the water processing multiplication and division problems, and realize the network that can shield the interrupt.
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Size: 93184 |
Author: 李敏 |
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Description: 详细具体的cpu设计maxplus源代码（附图）能完成cpu的基本功能。-Cpu design maxplus detailed and specific source code (with photos) to complete the basic functions of cpu.
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Size: 552960 |
Author: 自然 |
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