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[Modem programgsm0710.tar

Description: GSM07.10规范,串口复用协议。即在一个物理串口上建立多个逻辑连接,从而实现如 在gprs模块上同时进行短信和gprs数据收发同时进行。-GSM 07.10 is a multiplexer protocol specified by ETSI. It operates between a MS and a TE and allows a number of simultaneous sessions over a normal serial asynchronous interface. This permits, for example, sending of SMS from the TE while a data connection is in progress.
Platform: | Size: 211968 | Author: 彭圳 | Hits:

[Other Embeded programDan-Pian-Ji

Description: 单片机是一种集成在电路芯片,是采用超大规模集成电路技术把具有数据处理能力的中央处理器CPU随机存储器RAM、只读存储器ROM、多种I/O口和中断系统、定时器/计时器等功能(可能还包括显示驱动电路、脉宽调制电路、模拟多路转换器、A/D转换器等电路)集成到一块硅片上构成的一个小而完善的计算机系统。 -SCM is integrated in a circuit chip, is the use of very large scale integrated circuit technology have data processing capability of the central processor CPU ram, Rom ROM RAM, multiple I/O port, and interrupt system timer/timer function ( may also include a display drive circuit, a pulse width modulation circuit, analog multiplexer, A A/D converter circuit ) is integrated into a piece of silicon constitutes a small but perfect computer system.
Platform: | Size: 194560 | Author: 岳志新 | Hits:

[VHDL-FPGA-VerilogMux

Description: designing of multiplexer using vhdl language
Platform: | Size: 1024 | Author: sriramgopal | Hits:

[VHDL-FPGA-Verilogchoose

Description: 8-3多路选择器的fpga实现,数码管显示当前选择数据编号-8-3 multiplexer fpga realize, digital tube display the currently selected data Numbers
Platform: | Size: 9216 | Author: cc | Hits:

[VHDL-FPGA-Verilogmux4to1-1

Description: vhdl co of the multiplexer 4 to 1
Platform: | Size: 1048576 | Author: perfect22 | Hits:

[VHDL-FPGA-Verilogmux4to1-2

Description: --- vhdl code of multiplexer 4 to 1 ---- vhdl code of multiplexer 4 to 1 ---
Platform: | Size: 1048576 | Author: perfect22 | Hits:

[VHDL-FPGA-VerilogRISC_CPU

Description: VHDL语言设计的RISC_CPU,分为八个基本部件分模块构建,分别为时钟发生器,指令寄存器,累加器,算术逻辑运算单元,数据控制器,状态控制器,程序计数器以及地址多路器-The VHDL language RISC_CPU, is divided into eight basic components of modular construction, respectively, the clock generator, the instruction register, accumulator, arithmetic and logic unit, the data controller, the state controller, the program counter and address multiplexer
Platform: | Size: 6144 | Author: 林琳 | Hits:

[Com Port51moniduochuankou

Description: 51模拟多串口通信,解决内置串口数量不足问题-51 analog multiplexer serial communication, to solve the problem of built-in lack of serial number
Platform: | Size: 20480 | Author: 小周 | Hits:

[2D GraphicMARSim

Description: 模拟多能谱扇形束CT扫描,重建。基于Qt4平台、C++语言实现。-Analog multiplexer spectroscopy fan-beam CT scan reconstruction. Based on the the Qt4 platform, C++ language.
Platform: | Size: 20678656 | Author: 王军 | Hits:

[Software Engineeringmp2tsme-6.0.0

Description: The MP2TSME graphical user interface enables you to easily configure and multiplex a transport stream. At the core of MP2TSME is the robust and powerful Multiplexer. The Multiplexer verifies every transport stream with standard MPEG decoder buffer models as it is created to insure that it will be compliant.
Platform: | Size: 1294336 | Author: Mostafa | Hits:

[VHDL-FPGA-VerilogRISC-CPU

Description: 用FPGA实现一个简易的CPU,采用精简指令集结构,每一条指令有16bit,高三位为指令操作数,后13位为地址,该CPU能实现8种指令操作,分别有HLT(空一个中期)ADD(相加操作)SKZ(为零跳过)AND(相与操作)XOR(异或操作)LDA(读数据)STO(写数据)JMP(无条件跳转指令)。cpu包括8个部件,分别为时钟发生器、指令寄存器、累加器、算术逻辑单元、数据控制器、状态控制器、程序计数器、地址多路器,各个部件之间的相互操作关系由状态控制器来控制,程序指令存放在初始rom中,本例程存放在存储器初始文件中。 PS:为什么没有Verilog选项呢-A simple CPU, FPGA implementation to streamline the instruction set architecture, each instruction 16bit, high three operands for the instruction, the 13 address, the CPU can achieve the eight kinds of instruction operations, respectively, HLT (a medium-term empty) ADD (add operation) SKZ (zero skip) AND (phase operation) the XOR (exclusive OR operation) LDA (read data) STO (write data) JMP (unconditional jump instruction). cpu consists of eight parts, clock generator, the instruction register, accumulator, arithmetic logic unit, the data controller, the state controller, the program counter, the address multiplexer, the various components interoperate relations by the state controller to control, program instructions stored in the initial rom the routines stored in memory the initial file. PS: Why is there no Verilog options.
Platform: | Size: 3147776 | Author: vice | Hits:

[AlgorithmDesktop

Description: 包括3:8译码器,D触发器组成的8位寄存器,8位乘法器,41多路选择器。-Including 3:8 decoder, the D flip-flop composed of 8-bit registers, the 8-bit multiplier, 41 multiplexer selector.
Platform: | Size: 88064 | Author: 张易讯 | Hits:

[Driver Developussp_drivers.tar

Description: linux下GPRS/CDMA串口多路复用驱动源码,支持linux-2.6.29内核。-linux driver source code under the GPRS/CDMA serial multiplexer supports linux-2.6.29 kernel.
Platform: | Size: 10240 | Author: 刘一 | Hits:

[Software Engineeringcodlab-17-2-12

Description: Verilog programs- multiplexer, encoder etc
Platform: | Size: 3072 | Author: YESHASWINI H.S | Hits:

[Otherduolukaiguan

Description: 多路开关控制,基于51单片机控制的多路开关控制程序。-Multiple switch control, the multiplexer control procedures based on 51 single-chip control.
Platform: | Size: 6144 | Author: 夏勇 | Hits:

[Program docverilog_example

Description: verilog实例,多路器,除法器,数字跑表的多种实现方法-verilog example, the multiplexer, a divider, a digital stopwatch many implementations
Platform: | Size: 273408 | Author: 邹继超 | Hits:

[Home Personal applicationad

Description: ADC0809是美国国家半导体公司生产的CMOS工艺8通道,8位逐次逼近式A/D模数转换器。其内部有一个8通道多路开关,它可以根据地址码锁存译码后的信号,只选通8路模拟输入信号中的一个进行A/D转换。是目前国内应用最广泛的8位通用A/D芯片 -ADC0809 National Semiconductor production CMOS process 8-channel, 8-bit successive approximation A/D analog-to-digital converter. The interior of an 8-channel multiplexer switch, it can be decoded according to the address code latch signal gating one of the 8-channel analog input signal is A/D conversion. Is currently the most widely used 8-bit general purpose A/D chip
Platform: | Size: 11264 | Author: kidd | Hits:

[OtherTDM

Description: 八路异步数据统计复接器设计,按时分复用方式进行通信,阅读材料,非源代码-Octal asynchronous data statistical multiplexer design communication, reading material, source code, time division multiplexing
Platform: | Size: 115712 | Author: Jack | Hits:

[Software EngineeringCHU92A

Description: MIPS pipeline datapath Figure 6.30 in Paterson and Hennessy s textbook [4]. The model will be ... Listing 1.1: Verilog code for the multiplexer. A00000AA
Platform: | Size: 351232 | Author: he | Hits:

[VHDL-FPGA-Verilogmux2

Description: this is multiplexer gate in vhdl run under active hdl
Platform: | Size: 12288 | Author: sag | Hits:
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