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[Other resource] FPGAprogram5

Description: 数控振荡器的频率控制字寄存器、相位控制字寄存器、累加器和加法器可以用VHDL语言描述，集成在一个模块中，提供VHDL源程序供大家学习和讨论。 -NC oscillator frequency control word register, phase control word register, and processing instruments used accumulator can be used VHDL description, in an integrated modules provide VHDL source code for all learning and discussion.
Platform: | Size: 3844 | Author: 许嘉 | Hits:

[VHDL-FPGA-Verilog] FPGAprogram5

Description:
Platform: | Size: 3072 | Author: 许嘉 | Hits:

[VHDL-FPGA-Verilog] EDAdesign(4)

Description: 该文件中是关于一些VHDL许多编程实例以及源码分析，希望对VHDL爱好者有用。卷4包括低频数字相位测量仪、电压控制LC振荡器-The document is on a number of VHDL source code in many programming examples and analysis, in the hope that useful VHDL enthusiasts. Volume 4, including the low-frequency digital phase-measuring instrument, voltage-controlled LC oscillator
Platform: | Size: 1815552 | Author: shengm1 | Hits:

[VHDL-FPGA-Verilog] 1PPS

Description: 应用VHDL语言将高稳晶振分频得到1pps，使用GPS的1pps信号作为触发-Application of VHDL language high stability crystal oscillator frequency to be 1pps, the use of GPS signals as a trigger of 1pps
Platform: | Size: 34816 | Author: 党晓圆 | Hits:

[VHDL-FPGA-Verilog] CordicNCO

Description: 基于CORDIC算法的，数字控制振荡器的设计。带测试程序，输入一个振荡频率，输出SIN和COS的波形！-Based on the CORDIC algorithm, the digital controlled oscillator design. With test procedures, enter a oscillation frequency, the output waveform SIN and COS!
Platform: | Size: 4096 | Author: 咚咚 | Hits:

[VHDL-FPGA-Verilog] RomNCO

Description: 基于NCO的数字控制振荡器。带测试程序，输出12位的COS和SIN波形。-Based on the digital control oscillator NCO. With test procedures, the output 12 of the COS and the SIN waveform.
Platform: | Size: 29696 | Author: 咚咚 | Hits:

[assembly language] clock

Description: 数字钟是采用数字电路实现“时”、“分”、“秒”数字显示的计时装置。由于数字集成电路的发展和石英晶体震荡器的使用，使得数字钟的精度、稳定度远远超过了机械钟表，已成为人们日常生活中必不可少的必需品。-Digital Clock is a digital circuit implementation, " when" , " sub" , " second" The figures show that the timing device. Digital integrated circuits because of the development and use of quartz crystal oscillator, making the accuracy of the number of minutes, far exceeding the stability of mechanical clocks and watches, has become essential daily necessities.
Platform: | Size: 338944 | Author: 庄青青 | Hits:

[VHDL-FPGA-Verilog] DW8051_ALL

Description: 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!
Platform: | Size: 1588224 | Author: myfingerhurt | Hits:

[VHDL-FPGA-Verilog] CORDIC

Description: 数字控制振荡器（NCO，numerical controlled oscillator）是软件无线电、直接数据频 率合成器（DDS，Direct digital synthesizer）、快速傅立叶变换（FFT，Fast Fourier Transform） 等的重要组成部分，同时也是决定其性能的主要因素之一，随着芯片集成度的提高、在信号 处理、数字通信领域、调制解调、变频调速、制导控制、电力电子等方面得到越来越广泛的 应用。-Digital controlled oscillator (NCO, numerical controlled oscillator) is a software-defined radio, direct data on the frequency synthesizer (DDS, Direct digital synthesizer), Fast Fourier Transform (FFT, Fast Fourier Transform), such as an important component of the decision at the same time the performance of one of the main factors, along with the improvement of the chip integrated in the signal processing, digital communications, modulation and demodulation, frequency conversion speed control, guidance control, such as power electronics get more and more widely.
Platform: | Size: 4096 | Author: 司令 | Hits:

[Multimedia program] filter

Description: 数控振荡器用于产生可控的正弦波或余弦波。其实现的方法是查表法-CNC controlled oscillator used to generate the sine or cosine wave. Approach is the realization of look-up table method
Platform: | Size: 135168 | Author: 司令 | Hits:

[Printing program] thesis1

Description: thesis report related to vlsi area, specially for oscillator circuits
Platform: | Size: 1339392 | Author: renu raj garg | Hits:

[VHDL-FPGA-Verilog] counter

Description: 用VHDL语言实现的计时器，最大计时为24小时，计时精度为1ms，设有复位和暂停功能，使用的晶振频率为50Hz。-VHDL language implementation of the timer with a maximum time of 24 hours, timing accuracy of 1ms, with reset, and pause functions, using the crystal oscillator frequency is 50Hz.
Platform: | Size: 3072 | Author: 周峰 | Hits:

[Other] NCO

Description: Numerically Controlled oscillator with with quadrature output and pipeline-Numerically Controlled oscillator with with quadrature output and pipeline
Platform: | Size: 2048 | Author: sanjivkumar | Hits:

[VHDL-FPGA-Verilog] VCO_WITH_PLL

Description: Voltage controlled oscillator with p-Voltage controlled oscillator with pll
Platform: | Size: 2048 | Author: sai | Hits:

[Embeded Linux] 83390078DDS

Description: DDS的工作原理是以数控振荡器的方式产生频率、相位可控制的正弦波。电路一般包括基准时钟、频率累加器、相位累加器、幅度/相位转换电路、D/A转换器和低通滤波器（LPF）。频率累加器对输入信号进行累加运算，产生频率控制数据X（frequency data或相位步进量）。相位累加器由N位全加器和N位累加寄存器级联而成，对代表频率的2进制码进行累加运算，是典型的反馈电路，产生累加结果Y。幅度/相位转换电路实质上是一个波形寄存器，以供查表使用。读出的数据送入D/A转换器和低通滤波器。-DDS works the way we are digitally controlled oscillator frequency, phase controlled sine wave. Circuits generally include reference clock, frequency accumulator, phase accumulator, amplitude/phase converter circuit, D/A converter and low-pass filter (LPF). The frequency accumulator to accumulate the input signal operation to produce the frequency control data X (frequency data or phase stepping volume). From the N-bit phase accumulator and the N-bit full adder cascade accumulation register is made on behalf of the frequency of the two binary codes accumulation operation, is a typical feedback circuit, resulting in cumulative results of Y. Amplitude/phase converter circuit is essentially a waveform register for look-up table to use. Read out the data into the D/A converter and low pass filter.
Platform: | Size: 44032 | Author: 394177191 | Hits:

[assembly language] NCO

Description: 用VHDL语言编写的振荡器，可以产生正余弦信号-VHDL language with the oscillator, can generate sine and cosine signals
Platform: | Size: 1024 | Author: 龙兰飞 | Hits:

[VHDL-FPGA-Verilog] ISE_lab16

Description: 使用VHDL语言设计数字钟。 数字钟由晶振、分频器、计时器、译码器、显示器等组成-Digital clock design using the VHDL language. Digital clock from the crystal oscillator, frequency divider, timer, decoder, display and other components
Platform: | Size: 482304 | Author: zhangsheng | Hits:

[VHDL-FPGA-Verilog] Fenpin

Description: 基于VHDL语言时钟晶振48Mhz的分频器的制作能够实现1HZ分频的时钟信号。-48Mhz clock oscillator based on VHDL language to achieve the production of crossover frequency of the clock signal 1HZ.
Platform: | Size: 222208 | Author: 张帝 | Hits:

[VHDL-FPGA-Verilog] code

Description: it is the collection of the modules involved inthe design of digital fm.the code coves the key components like numerically controlled oscillator, loop filter, fir filter ,phase detector along with the complete cicuit implementation of the digital fm and the test bench of it.
Platform: | Size: 5120 | Author: syamprasad | Hits:

[VHDL-FPGA-Verilog] dpll

Description: 基于Verilog的数字锁相环。包括三个模块，数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
Platform: | Size: 668672 | Author: 栾帅 | Hits:
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