Search - phy verilog

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[Other resource] usb1.1phy DL : 0: USB 1.1 PHY的代码，verilog语言 USB 1.1 PHY的代码，verilog语言-USB 1.1 PHY code, verilog language USB 1.1 PHY code, verilog language
Update : 2008-10-13 Size : 8.55kb Publisher : william
[VHDL-FPGA-Verilog] usb1.1phy DL : 0: USB 1.1 PHY的代码，verilog语言 USB 1.1 PHY的代码，verilog语言-USB 1.1 PHY code, verilog language USB 1.1 PHY code, verilog language
Update : 2025-02-17 Size : 8kb Publisher : william
[VHDL-FPGA-Verilog] usb_phy DL : 1: umti协议中的usb1.1的verilog原文件，可公实现usb2.0做参考-umti the agreement usb1.1 verilog the original documents, the public can refer to achieve usb2.0
Update : 2025-02-17 Size : 10kb Publisher : liuzefu
[VHDL-FPGA-Verilog] POS_PHY_RTL DL : 0: VERILOG五POSPHY LEVEL3电路描述，可综合,已经过检验.-Five POSPHY LEVEL3 Verilog circuit description can be integrated, has been tested.
Update : 2025-02-17 Size : 61kb Publisher : 徐新颜
[VHDL-FPGA-Verilog] sata_device_model DL : 0: sata_device_model,对做硬盘控制器的朋友有帮助-sata_device_model, to make the hard disk controller has a friend help
Update : 2025-02-17 Size : 16.61mb Publisher : 磊
[VHDL-FPGA-Verilog] MAC DL : 0: Verilog code for MAC
Update : 2025-02-17 Size : 1mb Publisher : dheeru
[VHDL-FPGA-Verilog] mdio DL : 0: MDIO verilog RTL代码，SOC可以通过MDIO接口来访问外部PHY等慢速外设-MDIO verilog RTL code
Update : 2025-02-17 Size : 4kb Publisher : dingyy
[VHDL-FPGA-Verilog] smii_latest.tar DL : 0: SMII接口的mac控制器，通过测试。使用verilog语言！-The Serial Media Independent Interface, SMMI, is a low pin count version of the MII normally used between ethernet MAC and PHY. The Serial Media Independent Interface (SMII) is designed to satisfy the following requirements: Convey complete MII information between a 10/100 PHY and MAC with two pins per port allow multi port MAC/PHY communications with one system clock Operate in both half and full duplex per packet switching between 10 Mbit and 100 Mbit data rates allow direct MAC to MAC communication
Update : 2025-02-17 Size : 1011kb Publisher : weixin
[VHDL-FPGA-Verilog] mdio DL : 0: cpu与phy通信，让cpu能读写phy芯片，实现通信-cpu communication with phy
Update : 2025-02-17 Size : 2kb Publisher : sushaogang
[VHDL-FPGA-Verilog] USB_IP-CORE-design DL : 0: USB2.0的IP核，需要添加额外的PHY模块，使用Verilog语言编写-USB2.0 IP core, you need to add additional PHY module, using the Verilog language
Update : 2025-02-17 Size : 197kb Publisher : 董剑
[VHDL-FPGA-Verilog] MII DL : 0: 以太网MII芯片配置接口的VHDL设计，配置PHY芯片的模块设计-Ethernet MII chip configuration interface VHDL design, configuration PHY chip module design
Update : 2025-02-17 Size : 2kb Publisher : 雷伟林
[VHDL-FPGA-Verilog] MDIO DL : 0: 网络PHY88E1111的寄存器通讯协议的 verilog描述能实现 lookback 能读出PHY的资料-The register communication protocol Verilog description of the network PHY88E1111 lookback can read the PHY data
Update : 2025-02-17 Size : 1kb Publisher : tianfuhe
[VHDL-FPGA-Verilog] USB_fpga DL : 0: FPGA与USB PHY芯片Cy7c68013A通信的程序，Verilog语言-FPGA and USB PHY chip Cy7c68013A communication procedures, Verilog language
Update : 2025-02-17 Size : 4.17mb Publisher : 路永轲
[VHDL-FPGA-Verilog] K7_1M DL : 0: 用Verilog语言实现的以太网驱程，可最多实现8个以太网，外加PHY后，可实现ping操作-Ethernet drive-by Verilog language can achieve up to eight Ethernet, plus after PHY, can achieve a ping
Update : 2025-02-17 Size : 5.73mb Publisher : 罗军
[VHDL-FPGA-Verilog] sata_phy_latest.tar DL : 0: 用verilog写成的sata2的phy物理层，可应用与sata2的控制层下层接口！-Phy written by verilog sata2 the physical layer, the lower layer can be applied to the interface control layer and sata2!
Update : 2025-02-17 Size : 378kb Publisher : hezigang
[VHDL-FPGA-Verilog] SRIO-phy-code DL : 1: SRIO接口物理层的实现代码，非常复杂，完全自己用verilog编写，支持5G速率，可以作为开发参考-SRIO interface implementation code, the physical is very complex, completely written in verilog, support rate of 5 g, will be helpful to the development
Update : 2025-02-17 Size : 184kb Publisher : 小刚
[VHDL-FPGA-Verilog] udp_send1 DL : 0: 基于FPGA的UDP硬件协议栈，全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。支持外部phy的配置，支持GMII和RGMII模式。以下是接口 input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output wr_full, output [7:0] rd_data, input rd_clk, input rd_en, output rd_empty, input [31:0] local_ipaddr, //FPGA ip address input [31:0] remote_ipaddr, //PC ip address input [15:0] local_port, //FPGA port number //interface to ethernet phy output mdc, inout mdio, output phy_rst_n, output is_link_up, `ifdef RGMII_IF input [3:0] rx_data, output logic [3:0] tx_data, `else input [7:0] rx_data, output logic [7:0] tx_data, `endif input rx_clk, input rx_data_valid, input gtx_clk, output logic tx_en-UDP hardware stack, written in system verilog, do nt need CPU.Projgect includes MAC Layer,support phy configuration.support gmii and rgmii mode. the interface is as the follows: input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output wr_full, output [7:0] rd_data, input rd_clk, input rd_en, output rd_empty, input [31:0] local_ipaddr, //FPGA ip address input [31:0] remote_ipaddr, //PC ip address input [15:0] local_port, //FPGA port number //interface to ethernet phy output mdc, inout mdio, output phy_rst_n, output is_link_up, `ifdef RGMII_IF input [3:0] rx_data, output logic [3:0] tx_data, `else input [7:0] rx_data, output logic [7:0] tx_data, `endif input rx_clk, input rx_data
Update : 2025-02-17 Size : 52kb Publisher : qiubin
[VHDL-FPGA-Verilog] help_lib DL : 1: 1.JESD204B协议 2.Xilinx的JESD204B phy 核手册 3.Xilinx的JESD204B rx_tx 核手册7.1 4.Xilinx的JESD204B rx_tx 核手册7.2 5.verilog实现串口发送(1.JESD204B protocol 2.Xilinx JESD204B PHY core manual 3.Xilinx JESD204B rx_tx core manual 7.1 4.Xilinx JESD204B rx_tx core manual 7.2 5.verilog to achieve serial transmission)
Update : 2025-02-17 Size : 6.69mb Publisher : Nanke42
[Program doc] 14_ethernet_test DL : 0: 千兆网学习代码 ISE，状态机实现数据打包，基于PHY芯片实现数据传输(ethernet communication sample with verilog,state machine)
Update : 2025-02-17 Size : 6.78mb Publisher : konan007
[VHDL-FPGA-Verilog] DBSTAR_RGMII DL : 0: Verilog实现的RGMII和GMII接口转接，适合适配不同PHY芯片接口使用(Verilog implementation of RGMII and GMII interface transfer)
Update : 2025-02-17 Size : 4.9mb Publisher : zhzp

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