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[Other resource] fdpll

Description: 简单的可配置dpll的VHDL代码。 用于时钟恢复后的相位抖动的滤波有很好的效果， 而且可以参数化配置pll的级数。-simple configurable dpll VHDL code. Clock Recovery for the jitter filtering is a very good result, but can pll configuration parameters of the series.
Platform: | Size: 2037 | Author: 陈德炜 | Hits:

[Other resource] FractionalPLLDesign

Description: 是关于sigma delta PLL设计的详细论文，论文中有具体的设计细节，并在附录中有相应的matlab、vhdl code
Platform: | Size: 3802757 | Author: linxin | Hits:

[Other Databases] Xilinx-modelsim-library

Description: Xilinx的modelsim　仿真库！里面有许多库函数，对于ｖｌｏｇ或ｖｈｄｌ编程有很多好的源代码可以剪切！-Xilinx modelsim simulation library! There are many libraries, vlog or VHDL programming a lot of good source code can shear!
Platform: | Size: 32190464 | Author: 杨俊涛 | Hits:

[VHDL-FPGA-Verilog] fdpll

Description: 简单的可配置dpll的VHDL代码。 用于时钟恢复后的相位抖动的滤波有很好的效果， 而且可以参数化配置pll的级数。-simple configurable dpll VHDL code. Clock Recovery for the jitter filtering is a very good result, but can pll configuration parameters of the series.
Platform: | Size: 2048 | Author: 陈德炜 | Hits:

[Communication-Mobile] EXPT12_10_PHAS_PLL1

Description: VHDL 实现DDS的数字移相信号发生器的设计代码.直接解压打开就可以运行..自己写的代码-VHDL shifter DDS signal generator design code. Directly extract can run on open .. write their own code
Platform: | Size: 119808 | Author: haiou | Hits:

[VHDL-FPGA-Verilog] pll

Description: fpga中pll时钟实现的源代码，可实现倍频或分频-pll clock in the FPGA to achieve the source code, can be realized or sub-octave frequency
Platform: | Size: 3072 | Author: 张恒 | Hits:

[Post-TeleCom sofeware systems] Phase_Locked_Loop

Description: 对一般的PLL及APLL,定点PLL进行了MATLAB SIMULINK仿真，可以由程序直接生成PLL的VHDL和C源代码-General PLL and APLL, fixed-point MATLAB SIMULINK a PLL simulation, can be directly generated by the PLL of VHDL and C source code
Platform: | Size: 398336 | Author: joshua | Hits:

[VHDL-FPGA-Verilog] dpll_demo

Description: 一个实现简单的数字锁相环Verilog代码，本人借鉴网上现有的代码后经修改在Cyclone II上调通实现，里面有ModelSim仿真成功的波形图-A simple digital PLL Verilog code, I draw on-line after the existing code, as amended, pass upward in the Cyclone II realized, there are successful ModelSim Simulation Waveform
Platform: | Size: 67584 | Author: | Hits:

[matlab] FractionalPLLDesign

Description: 是关于sigma delta PLL设计的详细论文，论文中有具体的设计细节，并在附录中有相应的matlab、vhdl code-Is about the design of sigma delta PLL detailed papers, papers in the specific design details, and in the appendix corresponding matlab, vhdl code
Platform: | Size: 3802112 | Author: xin | Hits:

[VHDL-FPGA-Verilog] formatter

Description: Actel 基本VHDl模块源代码，包括BCD、LCD、PLL等-Actel basic VHDL source code modules, including BCD, LCD, PLL, etc.
Platform: | Size: 1024 | Author: 曾捷 | Hits:

[VHDL-FPGA-Verilog] PLL

Description: verilog PLL的代码，和PLL 的功能介绍，希望能通过，只是简单了点-verilog PLL code, and the function of PLL, the hope, but simply a point
Platform: | Size: 18432 | Author: gjj | Hits:

[Communication-Mobile] pll

Description: 实现同步时采用锁相环，锁相环实现的原理，及源代码，-Implementation of the principle of phase-locked loop, and the source code,
Platform: | Size: 111616 | Author: qin | Hits:

[Technology Management] dds9851

Description: 本文主要介绍的是采用直接数字频率合成的短波信号发生器，它主要以微电脑控制部分、直接数字频率合成（DDS）部分、数字锁相环频率合成部分、背光液晶显示部分、功率放大部分等组成。该软件系统采用菜单形式进行操作，操作方便明了，增加了很多功能。它通过启动DDS后，把内存缓存区的数据送到DDS后输出相应的频率，并把数据转换为BCD码，送到液晶显示器进行显示。该系统输出稳定度、精度极高，适用于当代的尖端的通信系统和精密的高精度仪器。-This paper describes the use of direct digital frequency synthesis of short-wave signal generator, which is part of a micro-computer control, Direct Digital Synthesis (DDS) of the digital part of PLL frequency synthesizer, backlit liquid crystal display of the power amplifier, etc. composition. The menu system uses the form of software to operate, easy to operate and clear, increase in the number of features. DDS through start after the memory cache after the data to the DDS output corresponding frequency, and the data is converted to BCD code to the LCD display. The output of the system stability, high precision for cutting-edge contemporary and sophisticated communication systems high-precision instruments
Platform: | Size: 466944 | Author: xiang | Hits:

[VHDL-FPGA-Verilog] FPGAPLL

Description: FPGA做的PLL 可以使用，比软件自带的省一些资源-PLL can be used FPGA to do more than the software comes with some of the resources of the province,
Platform: | Size: 112640 | Author: 李小虎 | Hits:

[VHDL-FPGA-Verilog] altpllpll

Description: 用VHDL语言编写的锁相环源代码，可用于配置FPGA，在FPGA中实现ＰＬＬ功能。-VHDL language with PLL source code, can be used to configure the FPGA, PLL function is implemented in the FPGA.
Platform: | Size: 3072 | Author: 王羽翾 | Hits:

[VHDL-FPGA-Verilog] DPLL

Description: 数字锁相环频率合成器的vhdl实现的源代码-Digital PLL Frequency Synthesizer vhdl source code to achieve
Platform: | Size: 539648 | Author: sunnyhp | Hits:

[VHDL-FPGA-Verilog] PLL.ZIP

Description: the code specifies how to model a pll using vhdl code
Platform: | Size: 6144 | Author: mridula | Hits:

[VHDL-FPGA-Verilog] VHDL-for-PLL.doc

Description: vhdl code for phase locked loop
Platform: | Size: 81920 | Author: datta | Hits:

[VHDL-FPGA-Verilog] SG_FPGA

Description: 2006年电子设计竞赛二等奖，多功能函数、信号发生器核心器件FPGA内部的原理图，主要模块用VHDL代码描述，包括PLL、相位累加器、波形算法和正弦波查找表，可实现0.005Hz~20MHz的多波形信号产生，频率步进值0.005，输出接100MSPS速率的DAC--AD9762-Electronic Design Competition 2006, second prize, multi-function signal generator within the core of the device schematic FPGA, VHDL code with the description of the main modules, including the PLL, phase accumulator, sine lookup table algorithm and the waveform can be realized 0.005Hz ~ 20MHz multi-waveform signal generator, the frequency step value of 0.005, then the output rate of 100MSPS DAC- AD9762
Platform: | Size: 1099776 | Author: zlz | Hits:

[VHDL-FPGA-Verilog] singnal

Description: VHDL实现通用通信信号源，包括sin，cos，方波，三角波，BPSK，GMSK，ASK，16QAM等信号的产生以及DDS，PLL的VHDL系统代码-VHDL implementation of universal communication sources, including sin, cos, square, triangle, BPSK, GMSK, ASK, 16QAM and other signal generation and DDS, PLL system, the VHDL code
Platform: | Size: 1024 | Author: 张泽端 | Hits:
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