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Description: 这是一个VHDL写的FIR模块，我的编译环境是QuartusII 5.0-This is a VHDL modules written FIR, I compiler environment is Quartus II 5.0
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Size: 8452 |
Author: 佴立峰 |
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Description: 使用Quartus II 5.0开发指导手册-use Quartus II 5.0 development guidance manual
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Size: 11830476 |
Author: KC_P |
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Description: 用CPLD控制图像卡进行帧存逻辑的verilog程序,用Quartus II 5.0打开-with CPLD control image frame buffer cards logical verilog procedures, Quartus II 5.0 Open
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Size: 1325 |
Author: 陈刚峰 |
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Description: adder4 hdl
ok
in
Quartus II 5.1
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Size: 4291 |
Author: emic |
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Description: cmi encoder
and decoder
ok in Quartus ii 5.1
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Size: 214994 |
Author: emic |
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Description: Quartus下的RS（5，3）编码器的源程序，用Verilog语言编写。
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Size: 3021 |
Author: 桃子 |
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Description: Compact Flash Support For Nios II 5.0, To download supporting materials for this new Compact Flash support, download the following .zip file, extract to a computer with Quartus II 5.0 & Nios II 5.0 installed, and proceed to use the hardware and/or software examples of your choice to proceed. Additional information is available in the readme.txt document, included in the top-level of the .zip file
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Size: 1589301 |
Author: Robert |
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Description: altera Quartus II 減法器使用
配合LED，可自動與手動按鈕控製。
(含電路)
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Size: 40423 |
Author: 陳小龍 |
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Description: Quartus II 5.0下写的一个单总线架构的CPU设计，包括控制器、运算器、译码电路等。模拟的时钟脉冲也给出。已经通过Quartus II 5.0运行。可以给需要设计总线架构CPU的同学一点参考。
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Size: 800692 |
Author: 陈佳 |
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Description: 这个给QuartusII初学者用的，里面很清楚的通过几个例子来告诉怎么运用QuartusII．
实验1：Quartus入门
实验2：简单的组合逻辑电路设计
实验3：七段数码管显示
实验4：BCD码显示及运
实验5：触发器和计数器
实验6：存储器的设计
实验7：基于DE2 的SOPC系统开发附录：
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Size: 755392 |
Author: yulieyar |
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Description: 在quartus 11 5.1 里用VHDL编写的正弦波发生器，经过仿真通过
Platform: |
Size: 246527 |
Author: 郭翠双 |
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Description: Altera的NIOS2SOPC平台上的音乐播放的软件模板。
Quartus 2版本5.0
Nios2 IDE版本5.0
硬件平台自己根据软件构建
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Size: 2788 |
Author: zt g |
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Description: 使用Quartus II设计并制作一台出租车计价器不同情况具有不同的收费标准行驶公里：
在行车三千米以内时，按起步价10元收费，超过3千米部分，以每千米1.6元计算。
l 途中等待（>2min 开始收费）
在等待时间小于2分钟以内时不收取额外费用，大于2分钟，按每分钟1.5元计算。
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Size: 69262 |
Author: yingzhua |
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Description: 基于Quartus II 5.0编写的正弦波发生器，可控频率，用vhdl编写的
Platform: |
Size: 475864 |
Author: uuk |
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Description: 使用Quartus II 5.0开发指导手册-use Quartus II 5.0 development guidance manual
Platform: |
Size: 11830272 |
Author: KC_P |
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Description: 用CPLD控制图像卡进行帧存逻辑的verilog程序,用Quartus II 5.0打开-with CPLD control image frame buffer cards logical verilog procedures, Quartus II 5.0 Open
Platform: |
Size: 1024 |
Author: 陈刚峰 |
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Description: 1)Learn more about the capabilities in Quartus:
2)Learn to use different design entry techniques
2)Design entry methods available within Quartus Text editor,Block diagram/schematic file editor,
Quartus interface with design entry/synthesis tools from Exemplar, Synopsys, Synplicity and Viewlogic
-1) Learn more about the capabilities in Qua rtus : 2) Learn to use different design entry techniqu es 2) Design entry methods available within Qua rtus Text editor, Block diagram/schematic file editor, Quartus interface with design entry/synthesi s tools from Exemplar, Synopsys. Synplicity and Viewlogic
Platform: |
Size: 2713600 |
Author: Jawen |
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Description: Compact Flash Support For Nios II 5.0, To download supporting materials for this new Compact Flash support, download the following .zip file, extract to a computer with Quartus II 5.0 & Nios II 5.0 installed, and proceed to use the hardware and/or software examples of your choice to proceed. Additional information is available in the readme.txt document, included in the top-level of the .zip file
Platform: |
Size: 1589248 |
Author: Robert |
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Description: 这是一个教你熟练使用Quartus 软件的过程 希望可以对大家有用 -This is a Quartus skilled in the use of the software you can hope to all useful process
Platform: |
Size: 1183744 |
Author: 龚淼 |
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Description: Quartus-II使用教程---图形输入(Quartus-II tutorial -- Graphical Input)
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Size: 1443840 |
Author: 阿联联联
|
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