Search - risc processor

[Embeded Linux] rtlinux__doc(2)

Description: ARM?系列微处理器作为全球 16/32 位 RISC 处理器市场的领先者，在许多领域内得到了成功的应用。近年来，ARM 在国内的应用也得到了飞速的发展，越来越多的公司和工程师在基于 ARM 的平台上面开发自己的产品。 -ARM microprocessor family as a global 16/32 bit RISC processor market leader, in many areas has been successfully applied. In recent years, the ARM in the applications has been developed rapidly, a growing number of companies and engineers based on the ARM platform above and develop its own products.
Platform: | Size: 220160 | Author: 另壶葱 | Hits:

[Other] RISC_processor_design

Description: RISC处理器设计简介 -RISC processor design brief profiles of RISC processor design
Platform: | Size: 232448 | Author: 湛斌 | Hits:

[Other Embeded program] ARM-emulator-2.1

Description: RISC processor ARM-7 emulator-ARM RISC processor-7 emulator
Platform: | Size: 192512 | Author: 侠克定 | Hits:

[STL] 1_TO_4

Description: 大型risc处理器设计源代码,这是书中的代码基于流水线的risc cpu设计-large risc processor design source code, which is based on the code book pipelined design of the risc cpu
Platform: | Size: 152576 | Author: | Hits:

[SCM] ARM_study_doc

Description: 介绍ARM的文档，对初学者很有用的，包含 32位RISC CPU ARM芯片的应用和选型.doc ARM7在嵌入式应用中启动程序的实现.doc ARM处理器与单片机性能价格比.doc ARM简介及编程.doc ARM开发调试教程.doc-on ARM documentation, very useful for beginners. includes 32-bit RISC CPU ARM chip application and selection. doc ARM7 Embedded Application start Implementation of procedures. doc ARM processor and SCM functional. doc profiles and the ARM program. doc ARM debugging Guide. doc
Platform: | Size: 71680 | Author: | Hits:

[VHDL-FPGA-Verilog] VCDwtHDLV

Description: < 大型RISC处理器设计--用描述语言Verilog设计VLSI芯片>>光盘-<Large RISC processor design- Verilog design language used to describe VLSI chip>> CD-ROM
Platform: | Size: 874496 | Author: wiyn | Hits:

[ARM-PowerPC-ColdFire-MIPS] simplesim-2.0.tar

Description: RISC处理器仿真分析程序。可以用于研究通用RISC处理器的指令和架构设计。在linux下编译，但也可在VC++中编译-RISC processor simulation analysis procedures. Can be used to study the generic RISC processor instructions and architecture design. In the compiler under linux, but can also be VC++ In compiler
Platform: | Size: 1152000 | Author: 吕奔 | Hits:

[VHDL-FPGA-Verilog] RISC_Core

Description: 这是用VerilogHDL描述的一个8位精简指令集处理器，包含完整代码，各种文档，以及测试环境。-This is described in VerilogHDL with an 8-bit RISC processor, including the integrity of the code, a variety of documents, as well as the test environment.
Platform: | Size: 316416 | Author: wdy2004 | Hits:

[VHDL-FPGA-Verilog] verilog_risc

Description: RISC状态机由三个功能单元构成：处理器、控制器和存储器。 RISC状态机经优化可实现高效的流水线操作。 RISC 中的数据线为16位。在数据存储器中的0到15的位置放置16个随机数，求16个数的和，放在数据存储器的16、17的位置，高位在前对这16个数进行排序，从大到小放置在18到33的位置求出前16个数的平均数，放在34的位置基本指令有NOP, ADD, SUB, AND, RD, WR, BR,BC。因为采用16位指令，有扩充的余地。-RISC state machine consists of three functional modules: processor, controller and memory. RISC state machine can be realized by optimizing the efficient pipelining. RISC data in line 16. In the data memory in the 0-15 position placed 16 random numbers, and the number 16 and, on the data memory of the 16,17 position, the previous high of 16 the number of these sort, smallest place in the 18-33 position to derive the average number of the top 16, on the location of 34 basic instructions are NOP, ADD, SUB, AND, RD, WR, BR, BC. Because the use of 16-bit instructions, there is room for expansion.
Platform: | Size: 129024 | Author: lyn | Hits:

[Program doc] dkljfkjls

Description: RISC处理器设计.ppt RISC处理器设计.ppt RISC处理器设计.ppt-RISC processor design. PptRISC processor design. PptRISC processor design. PptRISC processor design. PptRISC processor design. Ppt
Platform: | Size: 292864 | Author: appolo | Hits:

[VHDL-FPGA-Verilog] risc

Description: RISC（reduced instruction setcomputer，精简指令集计算机）是一种执行较少类型计算机指令的微处理器。改源码是vhdl语言，能在FPGA上跑。-RISC [reduced instruction setcomputer, Reduced Instruction Set Computer] is an implementation of fewer types of computer instructions to the microprocessor. VHDL source code are changed language in the FPGA on the run.
Platform: | Size: 9216 | Author: zhang | Hits:

[Editor] processor.tar

Description: i need of vhdl code for 32-bit risc processor
Platform: | Size: 48128 | Author: ganesh | Hits:

[VHDL-FPGA-Verilog] alu

Description: verilog code for alu in RISC processor
Platform: | Size: 1024 | Author: John jose | Hits:

[VHDL-FPGA-Verilog] RISC

Description: source and benchmark test for the registery parts of a RISC processor-source and benchmark test for the registery parts of a RISC processor
Platform: | Size: 158720 | Author: radproject | Hits:

[Other] MTK6225x

Description: MT6225 GSM/GPRS Baseband Processor Data Sheet The MT6225 is a highly integrated single chip solution for GSM/GPRS phone. Based on 32-bit ARM7EJ-STM RISC processor, MT6225 features not only high performance GPRS Class 12 MODEM but is also designed with support for the wireless multi-media applications, such as advanced display engine, synthesis audio with 64-tone polyphony, digital audio playback, Java acceleration, MMS and etc. Additionally, MT6225 provides varieties of advanced interfaces for functionality extensions, like 3-port external memory interface, 3-port 8/16-bit parallel interface, NAND Flash, IrDA, USB and MMC/SD/MS/MS Pro.
Platform: | Size: 5817344 | Author: HardWareMan | Hits:

[VHDL-FPGA-Verilog] RISC

Description: 32 bit RISC Processor with 3 stage pipeline
Platform: | Size: 2152448 | Author: rudra | Hits:

[VHDL-FPGA-Verilog] zxcpu

Description: 用VHDL语言设计了一个含10条指令的RISC处理器。假定主存可以在一个始终周期内完成依次读写操作且和CPU同步，系统使用一个主存单元。处理器指令字长16位，包含8个通用寄存器，1个16位的指令寄存器和一个16位的程序记数器。处理器的地址总线宽度16位。数据总线宽度16位，取指和数据访问均在一跳蝻数据总线。处理器支持包含LDA，STA，MOV，MVI，ADD，SUB，AND，OR，JZ，JMP十条指令。其中仅有LDA和STA是访存指令。-VHDL language design with a RISC processor with 10 instruction. Assume that main memory can be completed in one cycle is always followed and the CPU read and write operations and the synchronization system uses a main memory unit. 16-bit instruction word processor, including 8 general purpose registers, a 16-bit instruction register and a 16-bit program counter. Processor' s address bus width 16 bits. 16-bit data bus width, fetch and data access are in the hop hoppers data bus. Processor support includes LDA, STA, MOV, MVI, ADD, SUB, AND, OR, JZ, JMP ten instructions. LDA and STA is the only one memory access instructions.
Platform: | Size: 1076224 | Author: zhaoshu | Hits:

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[Embeded Linux] rtlinux__doc(2)

[Other] RISC_processor_design

[Other Embeded program] ARM-emulator-2.1

[STL] 1_TO_4

[SCM] ARM_study_doc

[VHDL-FPGA-Verilog] VCDwtHDLV

[ARM-PowerPC-ColdFire-MIPS] simplesim-2.0.tar

[VHDL-FPGA-Verilog] RISC_Core

[VHDL-FPGA-Verilog] verilog_risc

[Program doc] dkljfkjls

[VHDL-FPGA-Verilog] risc

[Editor] processor.tar

[VHDL-FPGA-Verilog] alu

[VHDL-FPGA-Verilog] RISC

[Other] MTK6225x

[VHDL-FPGA-Verilog] RISC

[VHDL-FPGA-Verilog] zxcpu

[VHDL-FPGA-Verilog] risc-processor

[Software Engineering] 1632-bit-RISC-processor-S3C2410A

[uCOS] 16-bit-risc-processor-master

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