Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - rom vhdl code

Search list

[VHDL-FPGA-Verilog] jop_rom

Description: JOP的RAM VHDL源码，经典的经典，不易找到的好东东，-JOP of RAM VHDL source code, classic classics, difficult to find a good price.
Platform: | Size: 4096 | Author: 黄肖超 | Hits:

[Communication-Mobile] GetRomData

Description: 生成4种方式的DDS输出的读表程序的VHDL源代码程序。-four ways generation of DDS output of the meter reading procedures VHDL source code procedures.
Platform: | Size: 176128 | Author: zhao | Hits:

[VHDL-FPGA-Verilog] ram

Description: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Platform: | Size: 2048 | Author: nick | Hits:

[Embeded-SCM Develop] CPLD234

Description: 文档中给出了使用VHDL编写的频率的精确测量方法的代码,同时还有cPLD与e2rom等的接口代码-Document given the frequency of the use of VHDL to prepare precise measurement method of the code, along with e2rom CPLD interface code, etc.
Platform: | Size: 223232 | Author: qibinchuan | Hits:

[VHDL-FPGA-Verilog] ise

Description: FPGA/CPLD设计工具---Xilinx ISE使用详解光盘源代码，Xilinx公司推荐的FPGA/CPLD培训教材-FPGA/CPLD design tools-Xilinx ISE explain the use of CD-ROM source code, Xilinx Inc. recommended FPGA/CPLD training materials
Platform: | Size: 22214656 | Author: 文成 | Hits:

[VHDL-FPGA-Verilog] rom

Description: 一个 16×8bit 的ROM程序包括程序的初始化。-A 16 × 8bit the ROM initialization procedures, including procedures.
Platform: | Size: 3072 | Author: h13978699183 | Hits:

[VHDL-FPGA-Verilog] rom

Description: 我用VHDL写的正弦，用FPGA内部ROM，有仿真testbench,在quartus里可以运行。在板子里已经验证-I used to write VHDL sinusoidal, using FPGA internal ROM, has simulation testbench, you can run in Quartus. Yard has already been verified in the plates
Platform: | Size: 651264 | Author: jimmy | Hits:

[VHDL-FPGA-Verilog] coswave

Description: 主要是通过Altera公司的Cuclone系列的FPGA-EP1C3T144C8产生余弦波的源代码 基于LPM-ROM余弦波一周期含有256个10位数据；-Mainly through Altera s Cuclone series of FPGA-EP1C3T144C8 cosine wave generated source code based on the LPM-ROM cosine wave of one cycle containing 256 10-bit data
Platform: | Size: 323584 | Author: 江俊 | Hits:

[VHDL-FPGA-Verilog] VHDL-ROM4

Description: 基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), waveform generator control module and latch module 2. Waveform data storage module (ROM) custom data width of 8 , address width of 6, can store 64 points sinusoidal waveform data, waveform data are obtained using MATLAB. 3. To 50MHz clock as input.
Platform: | Size: 98304 | Author: 宫逢源 | Hits:

[VHDL-FPGA-Verilog] rom

Description: 只读存储器VHDL代码，可运行实现，已用quartusII6.0验证-Read-only memory VHDL code can be run to achieve has been used to verify quartusII6.0
Platform: | Size: 1024 | Author: 干璐 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 《数字信号处理的FPGA实现》（第二版）光盘VHDL代码-" The FPGA digital signal processing to achieve" (second edition) CD-ROM VHDL code
Platform: | Size: 251904 | Author: 王昊 | Hits:

[Other] rom

Description: Turbo码编码器的Rom宏模块，此模块中包含Rom.v文件和存储交织地址的.mif文件-Turbo code encoder Rom macro module, this module contains intertwined Rom.v documents and store addresses. Mif file
Platform: | Size: 9216 | Author: sunhao | Hits:

[VHDL-FPGA-Verilog] Desktop

Description: VHDL code for 16 byte ROM & n bit comparator & a full adder
Platform: | Size: 1024 | Author: Davood | Hits:

[VHDL-FPGA-Verilog] RAM_Examples

Description: Verilog hdl code for representing ram and rom "memory" using many methods
Platform: | Size: 5120 | Author: Muftah | Hits:

[SCM] rom

Description: Rom的读取的Verilog代码，自己编写的，大家参考参考啊-Rom read the Verilog code, I have written, your information ah
Platform: | Size: 1024 | Author: keke | Hits:

[VHDL-FPGA-Verilog] VHDLcodes

Description: Behavioral description of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.- Behavioral description of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.
Platform: | Size: 6144 | Author: Vijay | Hits:

[VHDL-FPGA-Verilog] SPI_controller

Description: SPI serial flash ROM的verilog源代码, 针对winbond W25x16,已经经过逻辑验证,并实际用在芯片设计中,作为一个模块,正常工作.-SPI serial flash ROM in verilog source code for winbond W25x16, logic has been verified, and actually used in chip design, as a module to work.
Platform: | Size: 8192 | Author: Jerd Hu | Hits:

[VHDL-FPGA-Verilog] rom

Description: 该源码是基于查找表的VHDL代码实现DDS-The source code is based on the VHDL code look-up table DDS
Platform: | Size: 651264 | Author: allen-haha | Hits:

[VHDL-FPGA-Verilog] VHDL-node

Description: VHDL的一些实验代码，其中有4位可逆计数器，4位可逆二进制代码－格雷码转换器设计、序列检测器的设计、基于ROM的正弦波发生器的设计、数字密码锁的设计与实现-Some experiments of VHDL code, which has four reversible counters, four reversible binary code- Gray code converter design, sequence detection Design, ROM-based sine wave generator design, digital design and implementation of lock
Platform: | Size: 49152 | Author: 张联合 | Hits:

[Other Embeded program] VHDL-code-of-ROM-Based-Instruction-Memory

Description: code for 16 bit instruction memory
Platform: | Size: 1024 | Author: tarunsharma | Hits:
« 12 3 »

CodeBus www.codebus.net