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[VHDL-FPGA-Verilog] S6_VGA

Description: 我买的红色飓风FPGA,EP1C6开发板的配套USBA实验例程 VGA模块的程序-I bought a red hurricane FPGA, EP1C6 development board supporting VGA module USBA experimental routine procedures
Platform: | Size: 3191808 | Author: 孙建军 | Hits:

[Software Engineering] cpldpwm

Description: cpld的PWM输出控制，初学cpld良好例程-CPLD output of PWM control, a good beginner routine CPLD
Platform: | Size: 60416 | Author: 做人要厚道 | Hits:

[VHDL-FPGA-Verilog] Quartus2_VerilogRoutine

Description: 该文档是基于QUARTUS2_6.0的Verilog试验例程，其中附有工程源码，对于初学者是最好的例程！它是本人花费一年多自学后写的例程，以便初学者入门，里面附有很多图解，很详细！-The document is based on the Verilog test QUARTUS2_6.0 routines, including an engineering source code, for beginners is the best routine! It is, I spent more than a year after self-written routines in order to beginners entry, which accompanied by many diagrams, very detailed!
Platform: | Size: 4041728 | Author: 王斌 | Hits:

[Other] example10

Description: ：正弦波发生器例程，包括了直接数字频率合成(DDS)的原理以及如何应用CPLD产生频率可控频率的正弦信号。-: Sine wave generator routine, including a direct digital synthesizer (DDS), as well as the application of the principle of frequency control CPLD generated sinusoidal signal frequency.
Platform: | Size: 57344 | Author: 周平 | Hits:

[VHDL-FPGA-Verilog] SPI_IIC_design_example

Description: ALTERA原厂提供的例程，网上很难找到的，在MAX2系列芯片上实现过，VHDL和VERILOG两种语言编写 IIC读写程序-ALTERA provided the original routine, it is difficult to find online and in the MAX2 series chip-off, VHDL and VERILOG two languages
Platform: | Size: 394240 | Author: 郑康山 | Hits:

[VHDL-FPGA-Verilog] ss

Description: DE2开发板 sopc开发例程 友经科技提供-DE2 development board sopc the development of science and technology provided by the Friends of routine
Platform: | Size: 2324480 | Author: xinzhi | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 很全面的关于VHDL的编程程序库，里面有详细的例程，对一般用户编程，都会有很好的启示。-Very comprehensive programming on the VHDL library, which detailed the routine, the user programming in general, there will be a good inspiration.
Platform: | Size: 337920 | Author: xiapeng | Hits:

[VHDL-FPGA-Verilog] example1

Description: 本例程属于独立实验，主要是让大家熟悉一下VHDL 语言基本语法，这是比较简单的 程序了。实现一个将时钟信号clk 十分频的功能，可以通过波形仿真来看效果。 波形仿真的过程可以参考视频“波形仿真.exe”文件，有比较详细的操作方法。其实 在例程的项目中已经包含了波形仿真文件，大家可以直接仿真，观察结果。 -This routine is an independent experiment is designed to allow you familiarize yourself with the basic syntax of VHDL language, which is relatively simple program. To achieve a clock signal clk is the frequency of the function, you can look at the waveform simulation results. Waveform simulation process can refer to video " wave simulation. Exe" file, there is a more detailed method of operation. In fact, routine project already contains a waveform simulation file, we can direct simulation, observe the results.
Platform: | Size: 23552 | Author: 汤化锋 | Hits:

[VHDL-FPGA-Verilog] DM2_KX8051_FTEST_RS232_C5T

Description: 这是一个FPGA的简单例程，主要是基于FPGA的232串口通信的例程-This is a simple routine FPGA is mainly based on FPGA-232 serial communication routines
Platform: | Size: 445440 | Author: 万海 | Hits:

[DSP program] dsk5509a_v1

Description: Sectrum DSP 公司开发的5509DSP开发板，相对于国内的SEED公司要强的多，里面包括全部的电器原理图，例程说明，测试程序源码。对于设计DSP硬件电路板有很大的帮助！-Sectrum DSP development board developed by 5509DSP, compared to domestic companies stronger multi-SEED, which includes all of the electrical schematics, routine instructions, test procedures, source code. For the design of DSP hardware, circuit boards are a great help!
Platform: | Size: 4690944 | Author: 田野 | Hits:

[USB develop] usbFPGAconnect

Description: 该例程是PC机通过FX2-CY7C68013-A的USB2.0控制芯片与FPGA实现通信。其中的工程和代码包括PC机上的USB固件程序、驱动程序、上位机程序，FPGA上的VERILOG通信程序。-The routine is a PC, through the FX2-CY7C68013-A of the USB2.0 controller chip and the FPGA to achieve communication. One of the projects and code, including PC, the USB firmware, drivers, FPGA' s Communication Program
Platform: | Size: 7154688 | Author: 梁先国 | Hits:

[VHDL-FPGA-Verilog] FSK

Description: FSK编码器的实现例程 VHDL语言编写-FSK encoder to achieve routine VHDL language
Platform: | Size: 268288 | Author: Ivan_s | Hits:

[VHDL-FPGA-Verilog] circle

Description: VHDL routine to draw a circle using the midtpoint algorithm.
Platform: | Size: 2048 | Author: jcgcecilia | Hits:

[VHDL-FPGA-Verilog] led

Description: 定时器中断的例程，实现一秒定时，并在led灯上显示- Writes routine which a timer interrupts, realizes one second fixed time, and demonstrated on the led lamp
Platform: | Size: 3072 | Author: 蔡林 | Hits:

[VHDL-FPGA-Verilog] DE2

Description: terasic LTM+DE2 触摸屏例程-terasic LTM+ DE2 touch screen routine
Platform: | Size: 2935808 | Author: 张健 | Hits:

[VHDL-FPGA-Verilog] 8255

Description: 用VHDL实现8255并口板，是CPLD比较好的例程-8255 parallel port board with VHDL implementation is relatively good routine CPLD
Platform: | Size: 280576 | Author: 范立强 | Hits:

[VHDL-FPGA-Verilog] div

Description: 这是一个基于CPLD的VHDL语言的分频例程-This is a CPLD-based crossover routine VHDL language
Platform: | Size: 9216 | Author: 李朝 | Hits:

[VHDL-FPGA-Verilog] FPGA_BOOK

Description: 深入浅出玩转FPGA，作者吴厚航，由北京航空航天大学出版社出版。本书收集整理了作者在FPGA学习和实践中的经验点滴。书中既有日常的学习笔记，对一些常用设计技巧和方法进行深入探讨；也有很多生动的实例分析，这些实例大都是以特定的工程项目为依托，具有一定的借鉴价值；还有一些适合于初学者入门和进阶学习的实验例程；另外还给出了两个比较完整的DIY工程，让读者从系统角度理解FPGA的开发流程。 -Layman Fun FPGA, author Hou flight from Beijing Aerospace University Press. Book, the authors collected the FPGA to learn and practice experience bit by bit. The book not only the daily study notes on some common design techniques and methods in depth there are many vivid case studies, these examples are mostly based on specific projects as the basis, with some reference value some suitable Beginners and advanced study of the experimental routine also shows two relatively complete DIY project, so the reader from a system perspective to understand the FPGA development process.
Platform: | Size: 41352192 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] eeprom

Description: VERILOG实际例程，非常适合初学者学习-VERILOG the actual routine, ideal for beginners to learn
Platform: | Size: 521216 | Author: 王林 | Hits:

[VHDL-FPGA-Verilog] vhdl-Language-routine-highlights

Description: 工程中常用的VHDL控制模块，包括三态门，SDRAM，FIFO，PLL，RAM，FIlter等模块，非常实用的工程代码-Control module of VHDL is commonly used in engineering, including the tri-state gate, SDRAM, FIFO, PLL, RAM, FIlter module, very practical engineering code
Platform: | Size: 291840 | Author: shujian | Hits:
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