Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - rs Verilog

Search list

[SourceCode] RS编码verilog程序

Description: RS(Reed-Solomon)码是差错控制领域中一类重要的线性分组码，由于其出众的纠错能力，被广泛地应用于各种差错控制系统中，以满足对数据传输通道可靠性的要求。
Platform: | Size: 927 | Author: dafanxiaoqiao | Hits:

[Applications] RS encoder(Verilog)

Description: RS编码的源代码使用Verilog在Xinloinx平台-RS coding using the source code in Verilog Xinloinx platform
Platform: | Size: 5120 | Author: 王锋 | Hits:

[Embeded-SCM Develop] RS RS-232 至RS RS-485 RS RS-422 智能转换器

Description: RS RS-232 至RS RS-485 RS RS-422 智能转换器-RS RS-232 to RS RS-485 RS RS-422 Intelligent Converters
Platform: | Size: 159744 | Author: | Hits:

[VHDL-FPGA-Verilog] 结合XILINXCPLD RS232通信(verilog)

Description: 结合XILINXCPLD所做的模拟RS232通信verilog源程序-XILINXCPLD combine the simulation RS232 communication Verilog source
Platform: | Size: 121856 | Author: 于飞 | Hits:

[Communication] verilog for uart

Description: 通用异步接收器/发送器(UART)是能够编程以控制计算机到附加串行设备的接口的微芯片。详细来说,它提供给计算机RS-...还有高级的UART提供了一定数量的数据缓冲,这样计算机和串行设备数据流就可以保持同样的速度。-universal asynchronous receiver/transmitter (UART) can be programmed to control computer attached to the serial device interface microchips. Details, provide it to the computer RS-High ... UART also provide a certain number of data buffer, computer equipment and serial data stream can maintain the same speed.
Platform: | Size: 9216 | Author: 李志 | Hits:

[Other] rs-codec-8-16

Description: 这是一个rs译码器的verilog程序运行于quatus-This is a rs decoder running on Verilog quatus
Platform: | Size: 133120 | Author: yuanfeng | Hits:

[assembly language] rs-codec(255-223)

Description: 这是rs（255，223）编码的verilog源程序。里面有：encode、decode、test－bench等文件。-This is rs (255,223) verilog source coding. Inside : encode, decode, test-bench and other documents.
Platform: | Size: 18432 | Author: 陈 | Hits:

[ELanguage] rs-codec-8-4

Description: encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in decoder chien-search.v Chien search and Forney algorithm in decoder decode.v The top module of the decoder inverse.v Computes multiplication inverse of an Galois field element test-bench.v The test fixture, and some brief notes on using the modules. data-rom.v A simple data source for testing run For those intelligence-challenged who can t run verilog LGPL The license -encode.v syndrome.v Syndrome generator in decoder al berlekamp.v Berlekamp gorithm in decoder chien- search.v Chien searc h and Forney in decoder algorithm decode.v The t op module of the decoder inverse.v Computes intercommunication tiplication inverse of an element over Galois field test-bench.v The test fixture. and some brief notes on using the modules. data- rom.v A simple data source for testing run For th PNA intelligence-challenged who can not run veri The log LGPL license
Platform: | Size: 45056 | Author: zs8292 | Hits:

[VHDL-FPGA-Verilog] rs_decoder_31_19_6.tar

Description: Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1 Generator polynomial, g(x) = a^15 a^21*X + a^6*X^2 + a^15*X^3 + a^25*X^4 + a^17*X^5 + a^18*X^6 + a^30*X^7 + a^20*X^8 + a^23*X^9 + a^27*X^10 + a^24*X^11 + X^12. Note: a = alpha, primitive element in GF(2^5) and a^i is root of g(x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizable RTL modelling. Consists of 5 main blocks: SC (Syndrome Computation), KES (Key Equation Solver), CSEE (Chien Search and Error Evaluator), Controller and FIFO Register. -Hard-decision decoding scheme Codeword l KV (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents five bit. Uses GF (2 ^ 5) with primitive polynomial p (x) = x ^ x ^ 5 2 1 Ge nerator polynomial. g (x) = a ^ a ^ 15* 21 ^ 6 a X* X ^ a ^ 15 2* X ^ a ^ 3 25* X ^ a ^ 4 17 5* X ^ a ^ 18 ^ 6 X* a* X 30 ^ 7 ^ a ^ 20* X ^ a ^ 23 8* X ^ a ^ 9* 27 X 10 ^ a ^ 24* 11 ^ X ^ X 12. Note : a = alpha, primitive element in GF (2 ^ 5) and a ^ i is the root of g (x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizab le RTL modeling. Consists of five main blocks : SC (Syndrome Computation), KES (Key Equation Solver). CSEE (Chien Search and Error Evaluator) Controller and FIFO Register.
Platform: | Size: 14336 | Author: 许茹芸 | Hits:

[VHDL-FPGA-Verilog] RS(32to28)encoderanddecoder

Description: RS(32,28) encoder and decoder VHDL-RS (32,28) encoder and decoder VHDL
Platform: | Size: 76800 | Author: 王文 | Hits:

[VHDL-FPGA-Verilog] magnitude

Description: Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm. -Verilog HDL : For a vector magnitude (a, b), the magnitude representation is the following : A common approach to implementing thes e arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonome tric functions of sine, cosine, magn itude, and phase using an iterative process. It i 's made up of a series of micro-rotations of the v ector by a set of predetermined cons tants, which are powers of two. Using binary ar praxiology metic, this algorithm essentially replaces m ultipliers with shift and add operations. In a Stratix
Platform: | Size: 12288 | Author: 郝晋 | Hits:

[VHDL-FPGA-Verilog] uart_core_vhdlORverilog

Description: 串uart的vhdl，verilog，lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)\uart 源码 (Verilog)\uart 源码 (VHDL)\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) \ uart source (Verilog) \ uart source (VHDL) \ uart16550.tar
Platform: | Size: 294912 | Author: efly | Hits:

[VHDL-FPGA-Verilog] encode

Description: Quartus下的RS（5，3）编码器的源程序，用Verilog语言编写。-Quartus under the RS (5,3) encoder source code, using Verilog language.
Platform: | Size: 3072 | Author: 桃子 | Hits:

[VHDL-FPGA-Verilog] rs

Description: RS编码，verilog编写，可以自定义多项式，(255,233)和(204,188)均可。-RS coding, verilog prepared, can customize the polynomial, (255,233) and (204188) may.
Platform: | Size: 5120 | Author: sunwind | Hits:

[SCSI-ASPI] RSverilog

Description: RS编码的verilog源代码，拿来和大家分享-RS-coded Verilog source code, used to share
Platform: | Size: 2359296 | Author: 刘琼 | Hits:

[VHDL-FPGA-Verilog] RS(204_188)decoder

Description: <Verilog HDL 语言编程》 RS(204,188)译码器的设计-<Verilog HDL language programming RS (204,188) Decoder
Platform: | Size: 11264 | Author: 李映波 | Hits:

[VHDL-FPGA-Verilog] rs-codec-8-16

Description: RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
Platform: | Size: 27648 | Author: 饶进平 | Hits:

[Other] RS(204.188)design

Description: RS(204,188)译码器说明 原文件： rs_decoder.v（顶层文件）, SyndromeCalc.v（计算伴随式）, BM_KES.v（BM求解关键方程）, Forney.v（Forney算法求误差样值）, CheinSearch.v（搜索错误位置）,ff_mul.v（有限域乘法）。 ROM及初始化文件： rom_inv.v（求逆运算）, rom_power.v（求幂运算）； rom_inv.mif（ROM初始化文件）, rom_power.mif（ROM初始化文件）。 仿真波形： rs_decoder.vwf。-RS (204,188) decoder that the original document: rs_decoder.v (top-level document), SyndromeCalc.v (calculated Syndrome), BM_KES.v (BM key equation solving), Forney.v (Forney algorithm for error-like value), CheinSearch.v (search the wrong location), ff_mul.v (finite field multiplication). ROM and the initialization file: rom_inv.v (inverse operation), rom_power.v (for power calculations) rom_inv.mif (ROM initialization file), rom_power.mif (ROM initialization files). Simulation waveforms: rs_decoder.vwf.
Platform: | Size: 14336 | Author: 川天古木 | Hits:

[VHDL-FPGA-Verilog] RS-code

Description: 我测试过的！Verilog HDL实现RS编码。-I' ve tested it! RS coding Verilog HDL implementation.
Platform: | Size: 983040 | Author: kiekie | Hits:

[VHDL-FPGA-Verilog] RS

Description: RS译码器的设计源程序--verilog HDL实现-Design of the RS decoder source code-- Verilog HDL
Platform: | Size: 14336 | Author: 王垚 | Hits:
« 12 3 4 5 6 »

CodeBus www.codebus.net