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[Other resourcers

Description: RS编码,verilog编写,可以自定义多项式,(255,233)和(204,188)均可。
Platform: | Size: 4916 | Author: sunwind | Hits:

[Other resourceRS(204_188)decoder

Description: <Verilog HDL 语言编程》 RS(204,188)译码器的设计
Platform: | Size: 11406 | Author: 李映波 | Hits:

[SourceCode实用verilog代码(乘法器,触发器,FIFO等)

Description: 本文件包含一些实用verilog程序代码,包括乘法器,除法器,伽罗瓦域乘法器,CORDIC数字计算机的设计,异步FIFO设计,伪随机序列应用设计,RS(204,188)译码器的设计,都是可综合的。对研究这部分的朋友有一定的帮助。
Platform: | Size: 28867 | Author: zhanxin0319 | Hits:

[OtherVerilog HDL 语言编程 RS(204,188)译码器的设计

Description: Verilog HDL 语言编程 RS(204,188)译码器的设计源码
Platform: | Size: 11410 | Author: qinfeng | Hits:

[VHDL-FPGA-Verilogrs

Description: RS编码,verilog编写,可以自定义多项式,(255,233)和(204,188)均可。-RS coding, verilog prepared, can customize the polynomial, (255,233) and (204188) may.
Platform: | Size: 5120 | Author: sunwind | Hits:

[VHDL-FPGA-VerilogRS(204_188)decoder

Description: <Verilog HDL 语言编程》 RS(204,188)译码器的设计-<Verilog HDL language programming RS (204,188) Decoder
Platform: | Size: 11264 | Author: 李映波 | Hits:

[VHDL-FPGA-VerilogRSdecoder

Description: cpld/fpga RS(204,188)译码器的verilog程序-cpld/fpga RS (204,188) decoder of the Verilog program
Platform: | Size: 13312 | Author: 陈臣 | Hits:

[VHDL-FPGA-Verilogc23_RS_decoder

Description: 精通verilog HDL语言编程源码9——RS(204,188)译码器的设计-Proficient in verilog HDL source programming language 9- RS (204188) decoder design
Platform: | Size: 13312 | Author: 李平 | Hits:

[VHDL-FPGA-Verilogps

Description: RS(204,188)译码器的设计 异步FIFO设计 伪随即序列应用设计 CORDIC数字计算机的设计 CIC的设计 除法器的设计 加罗华域的乘法器设计-RS (204188) decoder design of asynchronous FIFO design application design sequence was pseudo-CORDIC design of digital computer design CIC divider design Le Hua domain multiplier design
Platform: | Size: 48128 | Author: 苏晓东 | Hits:

[matlabRS_code_decode

Description: RS纠错编码原理及其实现方法[第三版] 鉴于很多读者来信,特别是初学者对于如何求得RS生成多项式g[x]不是甚理解,特给出计算g[x]的MATLAB程序。-RS error-correcting coding theory and implementation methods [third edition] in view of a lot of letters from readers, especially for beginners on how to get RS to generate polynomial g [x] is not even understanding, give special calculation of g [x] in MATLAB procedures.
Platform: | Size: 1039360 | Author: 小陈 | Hits:

[Streaming Mpeg4rs_encode

Description: 这是用verilog编写的RS(204,188)代码,适用于数字电视的BCH编码过程。-This is the verilog prepared using RS (204,188) code, the application of digital television in the course of the BCH code.
Platform: | Size: 2048 | Author: 蕊宫獍雪 | Hits:

[OtherRS(204.188)design

Description: RS(204,188)译码器说明 原文件: rs_decoder.v(顶层文件), SyndromeCalc.v(计算伴随式), BM_KES.v(BM求解关键方程), Forney.v(Forney算法求误差样值), CheinSearch.v(搜索错误位置),ff_mul.v(有限域乘法)。 ROM及初始化文件: rom_inv.v(求逆运算), rom_power.v(求幂运算); rom_inv.mif(ROM初始化文件), rom_power.mif(ROM初始化文件)。 仿真波形: rs_decoder.vwf。-RS (204,188) decoder that the original document: rs_decoder.v (top-level document), SyndromeCalc.v (calculated Syndrome), BM_KES.v (BM key equation solving), Forney.v (Forney algorithm for error-like value), CheinSearch.v (search the wrong location), ff_mul.v (finite field multiplication). ROM and the initialization file: rom_inv.v (inverse operation), rom_power.v (for power calculations) rom_inv.mif (ROM initialization file), rom_power.mif (ROM initialization files). Simulation waveforms: rs_decoder.vwf.
Platform: | Size: 14336 | Author: 川天古木 | Hits:

[VC/MFCRS_code1

Description: RS编解码的C语言实现,译码是应用Berlekamp迭代译码-This program is an encoder/decoder for Reed-Solomon codes. Encoding is in systematic form, decoding via the Berlekamp iterative algorithm.
Platform: | Size: 4096 | Author: 吴雪 | Hits:

[VHDL-FPGA-VerilogverilogRS

Description: 该文件为基于fpga的RS(204.188)译码器的verilong源代码,使用的Quartus II的开发环境,已经通过编译,需要者可以自己下载在编译简历工程使用-The document is based on fpga' s RS (204.188) decoder verilong source code, use the Quartus II development environment, has been compiled by the need to download the compiler can resume their work using
Platform: | Size: 13312 | Author: bobo | Hits:

[Graph program1

Description: 图像处理,RS编码,纠错码这个单元对每个扰码后的传输数据帧,包括同 步字节进行截短的RS(204,188)编码.RS编码时, 在信息位前添加51字节的“0”再进入RS(255,239) 编码器,编码后再截去这些字节.RS(255,239)编码 -Image processing, RS coding, error correction code for each scrambling code of this unit after the transmission of data frames, including the sync byte truncated RS (204,188) code. RS encoding, the information bit before adding 51 bytes " 0 " and then enter the RS (255,239) encoder, encoding the bytes and then amputated. RS (255,239) coding
Platform: | Size: 1024 | Author: zrq | Hits:

[VHDL-FPGA-Verilogrs_encode

Description: 关于RS(204,188)的编码程序,已通过编译仿真。-On the RS (204,188) of the coding process has been simulated by compiled.
Platform: | Size: 329728 | Author: wangcimeng | Hits:

[VHDL-FPGA-VerilogRS_decode

Description: RS(204,188)译码,verlilog硬件描述语言的实现-rs decode
Platform: | Size: 14336 | Author: 张凤 | Hits:

[OtherRS_204_188

Description: DVB_T标准中的RS(204,188)的c仿真及实验报告-DVB_T standard in the RS (204,188) of the c simulation and experimental reports
Platform: | Size: 1312768 | Author: | Hits:

[VHDL-FPGA-VerilogRS(204188)

Description: RS(204,188)译码器的设计,经典实例,经过验证-RS (204,188) decoder design, the classic instance of proven
Platform: | Size: 15360 | Author: an | Hits:

[VHDL-FPGA-VerilogRS(204,188)译码器的设计

Description: RS(204,188)译码器说明 原文件: rs_decoder.v(顶层文件), SyndromeCalc.v(计算伴随式), BM_KES.v(BM求解关键方程), Forney.v(Forney算法求误差样值), CheinSearch.v(搜索错误位置),ff_mul.v(有限域乘法)。 ROM及初始化文件: rom_inv.v(求逆运算), rom_power.v(求幂运算); rom_inv.mif(ROM初始化文件), rom_power.mif(ROM初始化文件)。 仿真波形: rs_decoder.vwf。(RS (204188) decoder explanation Original document: Rs_decoder.v (top level file), SyndromeCalc.v (Computational adjoint), BM_KES.v (BM solving key equations). Forney.v (Forney algorithm for error sample), CheinSearch.v (search wrong location), ff_mul.v (finite field multiplication). ROM and initialization files: Rom_inv.v (inverse operation), rom_power.v (exponentiation operation). Rom_inv.mif (ROM initialization file), rom_power.mif (ROM initialization file). Simulation waveform: Rs_decoder.vwf.)
Platform: | Size: 15360 | Author: HelloFrank0 | Hits:
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