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[Other resourceVI2C_24A

Description: 本模拟I2C软件包包含了I2C操作的底层子程序,使用前要定义 好SCL和SDA。在标准8051模式(12 Clock)下,对主频要求是不高于12MHz(即1个 机器周期1us) 若Fosc>12MHz则要增加相应的NOP指令数。(总线时序符合I2C标 准模式,100Kbit/S)-simulation package contains the I2C operation of the bottom subroutine, prior to the use of a good definition of SCL and SDA. The standard model 8051 (12 Clock), the speed requirement is no more than 12MHz (that is, a machine cycle TI) if Fosc
Platform: | Size: 3151 | Author: ll | Hits:

[Other resourcevi2c_asm

Description: 非常好的一个I2C软件包。本模拟I2C软件包包含了I2C操作的底层子程序,使用前要定义 好SCL和SDA。在标准8051模式(12 Clock)下,对主频要求是不高于12MHz(即1个 机器周期1us) 若Fosc>12MHz则要增加相应的NOP指令数。(总线时序符合I2C标 准模式,100Kbit/S)
Platform: | Size: 2661 | Author: dfdf | Hits:

[WEB Codei2c.tar

Description: The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control and data transfer communication between ICs. Some of the features of the I2C bus are: • Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are required. A 12V supply line (500mA max.) for powering the peripherals often may be present. • Each device connected to the bus is software addressable by a unique address and simple master/ slave relationships exist at all times masters can operate as master-transmitters or as master-receivers. • The I2C bus is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer systems. • Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 KBit/s in the standard mode or up to 400 KBit/s in the fast mode.
Platform: | Size: 788781 | Author: lu | Hits:

[SCMVI2C_24A

Description: 本模拟I2C软件包包含了I2C操作的底层子程序,使用前要定义 好SCL和SDA。在标准8051模式(12 Clock)下,对主频要求是不高于12MHz(即1个 机器周期1us) 若Fosc>12MHz则要增加相应的NOP指令数。(总线时序符合I2C标 准模式,100Kbit/S)-simulation package contains the I2C operation of the bottom subroutine, prior to the use of a good definition of SCL and SDA. The standard model 8051 (12 Clock), the speed requirement is no more than 12MHz (that is, a machine cycle TI) if Fosc
Platform: | Size: 3072 | Author: ll | Hits:

[SCMvi2c_asm

Description: 非常好的一个I2C软件包。本模拟I2C软件包包含了I2C操作的底层子程序,使用前要定义 好SCL和SDA。在标准8051模式(12 Clock)下,对主频要求是不高于12MHz(即1个 机器周期1us) 若Fosc>12MHz则要增加相应的NOP指令数。(总线时序符合I2C标 准模式,100Kbit/S)-A very good package I2C. The simulation package includes I2C operation of the bottom of I2C subroutines, use the former to the definition of good SCL and SDA. 8051 in standard mode (12 Clock) under the requirements of the frequency is not higher than 12MHz (that is, a machine cycle 1us) if the Fosc
Platform: | Size: 2048 | Author: dfdf | Hits:

[Documentsi2c.tar

Description: The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control and data transfer communication between ICs. Some of the features of the I2C bus are: • Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are required. A 12V supply line (500mA max.) for powering the peripherals often may be present. • Each device connected to the bus is software addressable by a unique address and simple master/ slave relationships exist at all times masters can operate as master-transmitters or as master-receivers. • The I2C bus is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer systems. • Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 KBit/s in the standard mode or up to 400 KBit/s in the fast mode.
Platform: | Size: 788480 | Author: lu | Hits:

[Embeded-SCM Develop7290a

Description: 本模拟I2C软件包包含了I2C操作的底层子程序,使用前要定义 好SCL和SDA。在标准8051模式(12 Clock)下,对主频要求是不高于12MHz(即1个 机器周期1us) 若Fosc>12MHz则要增加相应的NOP指令数。(总线时序符合I2C标 准模式,100Kbit/S)。-The simulation package includes I2C operation of the bottom of I2C subroutines, use the former to the definition of good SCL and SDA. 8051 in standard mode (12 Clock) under the requirements of the frequency is not higher than 12MHz (that is, a machine cycle 1us) if the Fosc
Platform: | Size: 20480 | Author: huanghua | Hits:

[Software EngineeringVI2C_C51

Description: MCS-51单片机模拟I2C软件包本模拟I2C软件包包含了I2C操作的底层子程序,使用前要定义 好SCL和SDA。在标准8051模式(12 Clock)下,对主频要求是不高于12MHz(即1个 机器周期1us) 若Fosc>12MHz则要增加相应的NOP指令数。(总线时序符合I2C标 准模式,100Kbit/S)-MCS-51 Single-chip I2C simulation package
Platform: | Size: 6144 | Author: HUANGNANPING | Hits:

[Embeded-SCM DevelopI2C

Description: I2C显示程序,主要是通过SDA和SCL两个参数进行设置,数据的发送与接收。-I2C display program, mainly through the SDA and SCL set two parameters, the sending and receiving data.
Platform: | Size: 142336 | Author: 小飞 | Hits:

[assembly languagetuner

Description: 89c51控制I2C电视高频头今天成功制作了用89c51控制I2C电视高频头LCD显示。先做好51的最简单系统,然后P3口LCD,P2.0,P2.1,P2.2分别接LCD的R/S,R/W,E。P0.0,p0.1分别接高频头的SCL,SDA。-89c51 TV Tuner I2C control a successful production today with I2C control 89c51 TV tuner LCD display. 51 to do the most simple system, and then P3 mouth LCD, P2.0, P2.1, P2.2, respectively, then LCD' s R/S, R/W, E. P0.0, p0.1, respectively, then the first high frequency of SCL, SDA.
Platform: | Size: 4096 | Author: | Hits:

[Com Portuv916hex

Description: An RS232 port controls a TSA5512 via a PIC16F84 This allows a TV tuner to be scanned across its full range. 4MHz crystal for the PIC, the tuner has it s own internal crystal. Use a MAX232 for level shifting. SCL RB6 SDA RB5 Din RA1 Dout RA0
Platform: | Size: 1024 | Author: Nev | Hits:

[Software Engineeringsda55xx_design_guide_2an

Description: Micronas SDA 55xx TVText Pro Design Guide。 micronas公司的tv teletext设计资料,做电视机图文方案的很好参考-Micronas SDA 55xx TVText Pro Design Guide. micronas the company' s tv teletext design information graphics program to do a good TV Reference
Platform: | Size: 337920 | Author: wisebear | Hits:

[Other Embeded programshizhong

Description: 如果是用pc的串口传输数据就好办了,可以安装一个串口监视工具(如AccessPort)。电脑串口一般是2、3、5三根线通讯,2是txd,3是rxd,5是GND,但是电脑的逻辑电平与单片机的逻辑电平不同,具体看串口通信协议,网上很容易搜到。 IIC总线上的数据可以通过示波器查看,两个探头,一个连接clk,另一个连接sda,IIC通信时可以观察到传输的数据。 -If you are using pc' s serial port to transfer data much easier to handle, you can install a serial port monitoring tool (such as AccessPort). Computer port is generally 2,3,5 3 line communication, 2 is the txd, 3 is rxd, 5 is GND, but the computer and the microcontroller logic levels of different logic level, specifically to see the serial port communication protocols, the Internet is easy to search . IIC bus data can oscilloscope view, the two probes, a connection clk, another connection sda, IIC communication can be observed when the data transmitted.
Platform: | Size: 1024 | Author: 陈明宇 | Hits:

[VHDL-FPGA-VerilogI2C

Description: 语言:verilog 功能:用Verilog HDL编写的I2C主机串行通信的程序。两条总线线路:一条串行数据线 SDA, 一条串行时钟线 SCL;串行的 8 位双向数据传输位速率在标准模式下可达 100kbit/s,快速模式下可达 400kbit/s ,高速模式下可达 3.4Mbit/s;在数据传输过程中,当时钟线为高电平时,数据线必须保持稳定。如果时钟线为高电平时数据线电平发生变化,会被认为是控制信号。 仿真工具:modelsim 综合工具:quartus -Language: verilog Function: I2C written in Verilog HDL with the host serial communication program. Two bus lines: a serial data line SDA, a serial clock line SCL 8-bit bi-directional serial data transmission bit rate in the standard mode of up to 100kbit/s, fast mode, up to 400kbit/s, high-speed mode of up to 3.4Mbit/s in the data transmission process, when the clock line is high, the data line must remain stable. If the clock line is high level when the data line changes will be considered is the control signal. Simulation tools: modelsim synthesis tool: quartus II
Platform: | Size: 8192 | Author: huangjiaju | Hits:

[SCMRC522

Description: MFRC522串口通信1.硬件上将I2C,EA接低电平.2,SDA接CPU的TXD,D7接CPU的RXD.将3.3V电源也接入进来. 软件上将SPI收发改为串口收发,并将串口输出的寄存器地址也改为00XXXXXXb,10XXXXXXb的格式.通讯波特率采用默认的9600. -MFRC522 serial communication 1. Hardware will I2C, EA then low .2, SDA then CPU' s TXD, D7 CPU then the RXD. Will have access to come in 3.3V power supply. Transceiver to the serial SPI software will send and receive, and the serial output register addresses to 00XXXXXXb, 10XXXXXXb format. communication baud rate with default 9600.
Platform: | Size: 26624 | Author: 徐世军 | Hits:

[Game ProgramGPX

Description: 赛车。小游戏.做的不是很好,初学者,大家懂得,我就不必说了。-MY UD sj sdsd sds sd sda s d as
Platform: | Size: 4096 | Author: mallorca | Hits:

[matlabsda

Description: MATLAB构建的三段比幅式距离保护模型 内涵保护模块 S函数模块 -MATLAB built three-spoke distance protection model content protection module S function modules
Platform: | Size: 13312 | Author: 郑浩 | Hits:

[SCMIIC

Description: Inter-Integrated Circuit总线是由PHILIPS公司开发的两线式串行总线,用于连接微控制器及其外围设备 。它是同步通信的一种特殊形式,具有接口线少,控制方式简单,通信速率较高的特点。只需要一条串行数据线SDA,一条串行时钟线SCL 。它是一个真正的多主机总线,如果两个或更多主机同时初始化,数据传输可以通过冲突检测和仲裁防止数据被破坏;串行的8 位双向数据传输位速率在标准模式下可达100kbit/s,快速模式下可达400kbit/s,高速模式下可达3.4Mbit/s;连接到相同总线的IC 数量只受到总线的最大电容400pF 限制。SDA 线上的数据必须在时钟的高电平周期保持稳定。数据线的高或低电平状态只有在SCL 线的时钟信号是低电平时才能改变。串行数据SDA的下降沿和串行时钟SCL在稳定高状态时通信启动;SDA的上升沿和SCL在高电平时通信停止。数据传输必须带响应,相关的响应时钟脉冲由主机产生。在响应的时钟脉冲期间发送器释放SDA 线(高);在响应的时钟脉冲期间接收器必须将SDA 线拉低,使它在这个时钟脉冲的高电平期间保持稳定的低电平。通常被寻址的接收器在接收到的每个字节后,除了用CBUS 地址开头的数据,必须产生一个响应。-Inter-Integrated Circuit bus is a two-wire serial bus developed by PHILIPS company, used to connect the microcontroller and its peripherals. It is a special form of synchronous communication, and has a simple interface cable, the control mode, the communication rate is higher. Only need a serial data line SDA and a serial clock line SCL.It is a true multi-master bus, if two or more host initialization, data transfer by collision detection and arbitration to prevent data corruption serial 8-bit bidirectional data transfer rate up to the standard mode100kbit/s, the fast mode, up to 400kbit/s up to 3.4 Mbit/s high-speed mode IC number is only connected to the same bus by bus capacitance of 400pF limit. SDA line must remain stable in the high cycle of the clock. High or low state of the data lines only when the clock signal on the SCL line low to change. The falling edge of the serial data (SDA) and serial clock SCL in a stable high state communications start communication to stop the r
Platform: | Size: 3072 | Author: mary | Hits:

[SCMCH452W2

Description: 按键及数码管显示驱动芯片,调试通过,有中文备注。CH452的真正2线接口,含低电平脉冲按键中断在内,只需要2个I/O引脚,兼容I2C/IIC时序 两线制方式SCL/SDA,按键中断由SDA产生,接单片机的脉冲/边沿中断引脚 对于频率低于24MHz的MCS51,为了节约传输时间,可以适当减少SCL/SDA之间的延时-Buttons and digital display driver chip debugging through, Chinese Remarks. Including CH452 true 2-wire interface with low pulse button interrupt, only two I/O pin compatible I2C/IIC timing two-wire, SCL/SDA, key interrupt generated by the SDA, connected to the microcontroller' s pulse/edge interrupt pin for frequencies below 24MHz of the MCS51, in order to save transmission time can be appropriate to reduce the delay between the SCL/SDA
Platform: | Size: 1024 | Author: 李工 | Hits:

[Game ProgramGPX

Description: 赛车。小游戏.做的不是很好,初学者,大家懂得,我就不必说了。-MY UD sj sdsd sds sd sda s d as
Platform: | Size: 4096 | Author: gureou | Hits:
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