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[Other resource] AlteraSdramIP DL : 0: Altera Sdram IP 源码，VHDL写的
Update : 2008-10-13 Size : 763.33kb Publisher : 张敏
[Embeded-SCM Develop] 一些有用的IP核 DL : 1: 包含FIFO,LUT,SPMEM,DPMEM,SDRAM等常用IP核
Update : 2010-11-02 Size : 882.21kb Publisher : luckyzjian
[Embeded-SCM Develop] Bios DL : 0: S3C44BOX的BIOS。可使用的命令：help --- show help ? --- = help date --- show or set current date time --- show or set current time setweek --- set weekday clock --- show system running clock setmclk --- set system running clock setbaud ------ set baud rate ipcfg ------ show or set IP address load ------ load file to ram comload ------ load file from serial port run ------ run from sdram prog ------ program flash copy ------ copy flash from src to dst address boot ------ boot from flash backup ------ move bios to the top of flash md ------ show memory data move ------ move program from flash to sdram-S3C44BOX BIOS. Use the command : help show help------------------ = help show date set current date or time or set------ show current time setweek------ set weekday show------ clock system running clock setmclk------ set system running clock setbaud set baud rate------------ ipcfg show or set IP address load------ load file to ram comload------ load file from serial port run------ run from SDRAM prog------------ program flash copy copy from flash src dst address boot to boot from flash------------ backup bios move to the top of flash memory md show------------ move data move from program to flash SDRAM
Update : 2025-02-17 Size : 612kb Publisher : 付杰
[VHDL-FPGA-Verilog] sdram_ctrl.tar DL : 0: SDRAM控制IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-SDRAM control IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
Update : 2025-02-17 Size : 86kb Publisher : 周华茂
[VHDL-FPGA-Verilog] H1wQqGvI DL : 0: 详细介绍了ALTERA器件的IP CORE以及如何使用SDR SDRAM CONTROL-Described in detail ALTERA device IP CORE and how to use SDR SDRAM CONTROL
Update : 2025-02-17 Size : 759kb Publisher : 黄辉辉
[VHDL-FPGA-Verilog] AlteraSdramIP DL : 0: Altera Sdram IP 源码，VHDL写的-Altera Sdram IP source code, VHDL written
Update : 2025-02-17 Size : 763kb Publisher : 张敏
[VHDL-FPGA-Verilog] hssdrc_latest.tar DL : 0: HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License
Update : 2025-02-17 Size : 415kb Publisher : Arun
[VHDL-FPGA-Verilog] sdram_ver_134 DL : 0: This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is based Xilinx FPGA Playform.
Update : 2025-02-17 Size : 106kb Publisher : peace
[VHDL-FPGA-Verilog] sdram_vhd_134 DL : 0: This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is Verilog. This code is based Xilinx FPGA Playform.
Update : 2025-02-17 Size : 477kb Publisher : peace
[VHDL-FPGA-Verilog] AlteraSdramIP DL : 0: Altera Sdram IP 源码.rar-Altera Sdram IP source code. Rar
Update : 2025-02-17 Size : 707kb Publisher : hu71992
[VHDL-FPGA-Verilog] CPU11111 DL : 0: altera提供的sdram ip核例程，简单易懂。采用burst8模式。 -altera provided by the sdram ip core routines, easy to understand. Using burst8 model.
Update : 2025-02-17 Size : 1kb Publisher : 张寒枫
[VHDL-FPGA-Verilog] sdram DL : 0: how to use sdram ip ， just for fpga
Update : 2025-02-17 Size : 448kb Publisher : baoyu
[VHDL-FPGA-Verilog] DDR_SDRAM_design_and_conclusion DL : 0: DDR SDRAM总结文档，描述了DDR IP的设计挑战，接口时序，模块设计原则，调试技巧及应用指南-DDR SDRAM summary document describing the design challenge of DDR IP, interface timing, modular design principles, debugging skills and Application Guide
Update : 2025-02-17 Size : 331kb Publisher : 李中梅
[VHDL-FPGA-Verilog] sdram_ip_doc_preliminary DL : 0: 关于的SDRAM ip核相关资料汇总，SDRAM,SDRAM-On the SDRAM ip summary of nuclear-related materials, SDRAM, SDRAM
Update : 2025-02-17 Size : 361kb Publisher : zhaotao
[VHDL-FPGA-Verilog] SDRAM_ipcore_ DL : 0: Altera SDRAM ip核详解-Altera SDRAM ip nuclear Detailed
Update : 2025-02-17 Size : 1.59mb Publisher : fangyuanyong
[VHDL-FPGA-Verilog] DDR-SDRAM_IP_core DL : 0: DDR-SDRAM接口模块verilog源代码，可用作IP核使用，已在FPGA上验证-DDR-SDRAM interface module verilog source code, can be used as IP cores to use, proven
Update : 2025-02-17 Size : 463kb Publisher : zyy
[VHDL-FPGA-Verilog] SDR_SDRAM_IP DL : 0: SDR SDRAM 控制器，Altera官网重要资料。内涵说明文档，和VHDL与Verilog两种设计IP。-SDR SDRAM controller from Altera
Update : 2025-02-17 Size : 2.25mb Publisher : peteryu010
[Other] sdr-sdram-verilog DL : 0: SDRAM IP CORE,ALTERA提供-SDRAM IP CORE,ALTERA
Update : 2025-02-17 Size : 1.22mb Publisher : wushj
[Other] Altera-SDRAM_controller-IP-CORE DL : 0: Altera的SDRAM IP核代码，支持源码创作-Altera s SDRAM IP core code to support the creation of source
Update : 2025-02-17 Size : 3.34mb Publisher : chen600
[VHDL-FPGA-Verilog] Sdram DL : 0: 在vivado中调用SDRAM的IP核，并通过数据的读入，读出，验证IP核的使用，文件中有仿真结果时序图。(In the vivado call SDRAM IP core, and read through the data, read, verify the use of IP kernel, the file has simulation results sequence diagram.)
Update : 2025-02-17 Size : 49kb Publisher : 01121100

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