Search - shift left

[Other resource] left-rightled

Description: 本Program 左右移循环流水灯-recirculating shift lights
Platform: | Size: 2044 | Author: 彭长庚 | Hits:

[SCM] left-rightled

Description: 本Program 左右移循环流水灯-recirculating shift lights
Platform: | Size: 2048 | Author: 彭长庚 | Hits:

Description: 移位寄存器,异步清零,异步置数,左移右移可控,具有循环移位功能-Shift Register, Asynchronous Clear, asynchronous purchase the number of controllable left shifted to right with a cyclic shift function
Platform: | Size: 197632 | Author: 郭明 | Hits:

[VHDL-FPGA-Verilog] shift_register

Description: -- DESCRIPTION : Shift register -- Type : univ -- Width : 4 -- Shift direction: right/left (right active high) -- -- CLK active : high -- CLR active : high -- CLR type : synchronous -- SET active : high -- SET type : synchronous -- LOAD active : high -- CE active : high -- SERIAL input : SI-- DESCRIPTION: Shift register- Type: univ- Width: 4- Shift direction: right/left (right active high )---- CLK active: high- CLR active: high- CLR type: synchronous-- SET active: high- SET type: synchronous- LOAD active: high- CE active: high- SERIAL input: SI
Platform: | Size: 1024 | Author: sanshanchuns | Hits:

[Special Effects] yuv-rw

Description: openyuv.m将yuv视频文件打开，保存为png文件。writeyuv.m将yuv视频中的第一镇上/下/左/右位移后写入另一yuv文件。-openyuv.m will yuv video file open, save as a png file. yuv video writeyuv.m will be the first town/down/left/right shift after another yuv file write.
Platform: | Size: 1024 | Author: 张红 | Hits:

[VHDL-FPGA-Verilog] EX

Description: Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
Platform: | Size: 4096 | Author: hugo | Hits:

[VHDL-FPGA-Verilog] 1_LAB

Description: Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
Platform: | Size: 6119424 | Author: hugo | Hits:

[OS program] PTMateMain_Src

Description: Dev C++ 4.9.9.2 File Tree: | +---PTMateMain.dev(Work Space) +---dllmain.cpp(Main Working File) +---dll.h(Main Header File) +---*.rc(Resource Files) +---other header files | +-Functions | +----Funcs.cpp (Main Hacking Functions) | +----Funcs.h (the header) | +-MemSearch | +----MemSearch.a(Address Locating Lib) | +----MemSearch.h(the header) Functions&Hot Keys: Control+F1: Shop Window Control+F2: Artisan Window Control+F3: Smith Window Control+F4: Store House Control+F5: Force Great Control+F6: Skill Master Control+F7: Reset Attribute Control+F8: Reset Skill Shift+F1: Skill Without Delay, MP and SP Shift+F2: Quick Restore HP Shift+F3: Auto Right Click Shift+F4: Light Up at Night Shift+F5: Effect Skill For Archers Shift+F6: Plus Exp ％30 Shift+F7: Teleport Shift+F8: Full Screen Attack Control + Direction Keys For moveing by Axis Shift + Up&Down For Flying&Skill Trainning.. Shift + LEFT&RIGHT For Modifying Teleport Number-Dev C++ 4.9.9.2File Tree: |+--- PTMateMain. Dev (Work Space)+--- Dllmain. Cpp (Main Working File)+--- Dll. H (Main Header File) 2B !---*. rc (Resource Files)+--- other header files |+-Functions | 2B !---- Funcs.cpp (Main Hacking Functions) | 2B !---- Funcs.h (the header) |+-MemSearch | 2B !---- MemSearch.a (Address Locating Lib) | 2B !---- MemSearch.h (the header) Functions
Platform: | Size: 71680 | Author: fwefwef | Hits:

[VHDL-FPGA-Verilog] shift_register

Description: 用Verilog实现的移位寄存器，可以实现左移、右移等功能-Using Verilog implementation of the shift register, you can achieve the left, shifted to right and other functions
Platform: | Size: 3072 | Author: huhahuha | Hits:

[Windows Develop] T3_1

Description: 一个4比特移位寄存器,活跃在不断上升的边缘的时钟。登记应能转移左、右移,接受连续剧和平行(负荷)输入,而有一个异步预设(“1111”)和清晰的(“0000”)的能力。-a 4-bit shift register which is active on the rising edge of the clock. The register should be able to shift left, shift right, accept a serial and parallel (load) input, and have an asynchronous preset (“1111”) and clear(“0000”) capability.
Platform: | Size: 26624 | Author: sunzhongyuan | Hits:

[VHDL-FPGA-Verilog] homework32

Description: 这是32位移位寄存器，是用verilog编写的，能够实现从1到31位的左或右的移位-This is a 32-bit shift register, is prepared verilog, can be realized from the 1-31 shift left or right
Platform: | Size: 2048 | Author: 杨恋 | Hits:

[VHDL-FPGA-Verilog] shifter

Description: vhdl,双向移位寄存器，实现置数，左移及右移操作-vhdl, bi-directional shift register to achieve set the number of left and right shift operation
Platform: | Size: 32768 | Author: 王晓虎 | Hits:

[VHDL-FPGA-Verilog] unishift

Description: An universal shift register performs the following tasks load, right shift ,left shift and parallel load as the selection inputs are 00,01,10,11 respectively. Such a register is implemented here in Quartus.
Platform: | Size: 1024 | Author: sidd | Hits:

[VHDL-FPGA-Verilog] shifter

Description: 8位移位器，实现算术左、右移位，逻辑左右移位和循环左右移位。-8-bit shift device to achieve arithmetic left and right shift, logical shift left shift and cycle around.
Platform: | Size: 215040 | Author: 龙一 | Hits:

[VHDL-FPGA-Verilog] 8multipler

Description: 用VHDL实现8位移位相加乘法器，从被乘数的最低位开始，若为1，则乘数左移后与上次的和相加；若为0，左移后以全0相加，直至被乘数的最高位。-VHDL 8-bit shift by adding the multiplier to achieve, starting from the lowest multiplicand, if 1, then left after the multiplier and add the last if 0, left after adding all 0, until the highest bit multiplicand.
Platform: | Size: 1024 | Author: ruanxioafei | Hits:

[Windows Develop] 77777

Description: MFC利用CTRL+SHIFT+鼠标左键同时按下的情况下，运行结果会根据你所按下的键弹出按键的情况，程序有点狭隘，改动即可实现任意键的提示。-MFC using CTRL+ SHIFT+ left mouse button while pressing the case, the results will be based on the key you press the eject button, the program a bit narrow, change any key tips can be realized.
Platform: | Size: 1989632 | Author: 黄强 | Hits:

[Delphi VCL] delphi7

Description: 1.SHIFT+鼠标左键先选中任一控件,按键后可选中窗体(选中控件后按Esc效果一样) -1.SHIFT+ left mouse button to select any one of the first control, after the optional key in the form (select the same effect as the control, press Esc)
Platform: | Size: 2048 | Author: 杨程 | Hits:

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[Other resource] left-rightled

[SCM] left-rightled

[VHDL-FPGA-Verilog] shift

[VHDL-FPGA-Verilog] shift_register

[Special Effects] yuv-rw

[VHDL-FPGA-Verilog] EX

[VHDL-FPGA-Verilog] 1_LAB

[OS program] PTMateMain_Src

[VHDL-FPGA-Verilog] shift_register

[Windows Develop] T3_1

[VHDL-FPGA-Verilog] homework32

[VHDL-FPGA-Verilog] shifter

[VHDL-FPGA-Verilog] unishift

[VHDL-FPGA-Verilog] shifter

[VHDL-FPGA-Verilog] 8multipler

[Windows Develop] 77777

[Delphi VCL] delphi7

[VHDL-FPGA-Verilog] Shift

[SCM] led_left-shift

[Software Engineering] shift-left-register-8-bit

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