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[VHDL-FPGA-Verilog] LFSR

Description: 自动生成线形反馈移位寄存器的各种HDL源代码和原理图的工具-Automatic generation of linear feedback shift register of a variety of HDL source code and schematic tools
Platform: | Size: 162816 | Author: zx | Hits:

[VHDL-FPGA-Verilog] homework32

Description: 这是32位移位寄存器，是用verilog编写的，能够实现从1到31位的左或右的移位-This is a 32-bit shift register, is prepared verilog, can be realized from the 1-31 shift left or right
Platform: | Size: 2048 | Author: 杨恋 | Hits:

[VHDL-FPGA-Verilog] HDB3

Description: 用verilog HDL语言，通过一个4位移位寄存器实现一个信号转化为HDB3码并进行测试 -Using verilog HDL language, through a 4-bit shift register realization of a signal into HDB3 code and test
Platform: | Size: 1024 | Author: 空 | Hits:

[VHDL-FPGA-Verilog] shifter

Description: verilog实现的“并行输入、并行输出移位寄存器”-verilog to achieve a " parallel input, parallel output shift register"
Platform: | Size: 1024 | Author: 王先生 | Hits:

[VHDL-FPGA-Verilog] shiftrot

Description: A verilog hdl code for rotational shift register
Platform: | Size: 36864 | Author: z | Hits:

[Windows Develop] LFSR

Description: verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) module. Has passed modelsim simulation.
Platform: | Size: 870400 | Author: 风影 | Hits:

[VHDL-FPGA-Verilog] register-vcode

Description: shift register verilog code
Platform: | Size: 6144 | Author: praveen | Hits:

[VHDL-FPGA-Verilog] ass1_2_hamming

Description: Hamming codes are a class of binary linear codes. They can detect up to two simultaneous bit errors, and correct single-bit errors. In particular, a single-error-correcting and double error detecting variant commonly referred to SECDED.-a) Develop a Verilog module that will generate a 7-bit encoded data from a 4-bit data. Simulate your design for two inputs. Use even or odd parity according to the least significant figure of your ID number. b) Develop a Veriog module for generating pseudorandom 4-bit data using Linear Feedback Shift Register( LFSR) method. c) Develop a Verilog module to emulate one bit error in the data transmission. This can be done by changing only one of the encoded bits at each clock cycle. You may use a ring-counter and XOr gates for doing this. This arrangement will insert error in consecutive bits at each clock cycle. d) Design a Hamming error detection and correction circuit to restore the original data. e) Compare the original data with the restored data to verify the error correction capability of your design. If the two data sets are equal an OK signal will be set.
Platform: | Size: 1133568 | Author: wei chenghao | Hits:

[VHDL-FPGA-Verilog] register

Description: 用Verilog语言写一个简单的移位寄存器，可以进行算术移位和逻辑移位。-Verilog language used to write a simple shift register, can be arithmetic shift and logical shift.
Platform: | Size: 314368 | Author: sunying | Hits:

[VHDL-FPGA-Verilog] par_in_par_out

Description: 并入并出双向移位寄存器，很好很强大。使用Verilog进行设计并用Modelsim成功仿真。-Into the shift register and a two-way, very very strong. With Verilog for design and simulation using Modelsim successfully.
Platform: | Size: 1269760 | Author: iswl2009 | Hits:

[VHDL-FPGA-Verilog] password

Description: verilog代码实现的数字密码锁。通过4个并行的10位移位寄存器，分别记录在时钟上升沿时A,B,C,D的输入情况，比如某上升沿输入A，相应时刻A对应的移位寄存器输入1，其他三个移位寄存器输入都为0.另外4个并行的10位寄存器记录密码。这样，密码锁不仅可以识别字符数量，还可以判断出字符的输入次序。-verilog code of digital lock. By four parallel 10-bit shift register, respectively, recorded in the clock rising edge A, B, C, D of inputs, such as a rising edge of input A, the corresponding moments A 1 corresponding to the input shift register, the other three shift bit register inputs are 0. another four parallel 10-bit registers record the password. This lock can not only identify the number of characters, you can also determine the character of the input sequence.
Platform: | Size: 578560 | Author: 陈振睿 | Hits:

[VHDL-FPGA-Verilog] Shift_reg

Description: 一个简单移位寄存器代码，verilog HDL编写-a simple shift register example，write with verilog HDL
Platform: | Size: 1061888 | Author: FEIFEI | Hits:

[VHDL-FPGA-Verilog] RSN

Description: “Randomized Smoothing Networks” introduced the idea of using networks composed of a type of comparator/memory element, initialized to random initial states, to create smoothing networks, which take arbitrary input loads into the network and produce an output that balances the load among all the outputs in a predictable manner. I created a synthesizable Verilog model of these comparator/memory elements (or “balancers”), and used a pseudo-random linear feedback shift register (LFSR) to toggle all possible initial random states for two of the proposed RSNs configurations, the Block network and the Butterfly network, verifying the results of Herlihy and Tirthapura.
Platform: | Size: 247808 | Author: Stephen Bishop | Hits:

[MPI] rank_int

Description: Verilog写的产生32位随即数。通过seed产生随即数起始。通过线性反馈移位寄存器产生随机数。 -32 Verilog write the generated random number. Starting seed generated random number. By a linear feedback shift register to generate random numbers.
Platform: | Size: 835584 | Author: sn | Hits:

[VHDL-FPGA-Verilog] testbench_learn

Description: 自己写的一个移位寄存器的实例，该例子主要用来讲述verilog中的testbench的写作，以及在testbench中怎样使用task，以使仿真更加的高效简洁-Write your own instance of a shift register, which is mainly used to describe examples of verilog testbench writing, as well as how to use the testbench in the task, to make the simulation more simple and efficient
Platform: | Size: 3072 | Author: 雷 | Hits:

[VHDL-FPGA-Verilog] Lab12_shiftreg

Description: 4位移位寄存器的设计与实现.本实验中用Verilog语句来描述。nexy3.-Design and implementation of a 4 bit shift register. The Verilog statement in this experiment to describe. Nexy3
Platform: | Size: 207872 | Author: penglx1803 | Hits:

[Software Engineering] SHIFT-RESISTER.tar

Description: its about a shift register design using verilog and verification using system verilog files for uvm.
Platform: | Size: 348160 | Author: ladu | Hits:

[VHDL-FPGA-Verilog] 8_1

Description: 一个具有置位、复位、左移和右移功能的八位移位寄存器/“01011010”序列检测器。移位寄存器电路端口为：异步清零输入端口rst，输入时钟clk，置数判断输入端口load，移位类型判断输入端口m，数据输入端口data[7:0]，输出端口q[7:0]。序列检测器电路端口为：异步清零输入端口rst，输入时钟clk，串行数据输入端口d，输出标志端口s。(A eight bit shift register / 01011010 sequence detector with set, reset, left shift, and right shift function. Shift register circuit port is: Asynchronous Clear input port rst, input clock CLK, set the number to determine the input port load, shift type to determine the input port m, data input port data[7:0], output port q[7:0]. The sequence detector circuit port is: Asynchronous Clear input port rst, input clock CLK, serial data input port D, output flag port s.)
Platform: | Size: 94208 | Author: 白学 | Hits:

[VHDL-FPGA-Verilog] random

Description: 用简单的线性反馈移位寄存器实现了伪随机数的生成…(The pseudo random number is generated by a simple linear feedback shift register)
Platform: | Size: 740352 | Author: fv_4 | Hits:

[assembly language] Verilog源代码

Description: 多种基本功能的Verilog代码实现，包括多路选择器，二进制到BCD码转换，二进制到格雷码转换，7段译码器，8位数据锁存器，移位寄存器等等多种功能。(Verilog code implementation of a variety of basic functions, including multiplexer, binary to BCD code conversion, binary to Gray code conversion, 7-segment decoder, 8-bit data latch, shift register and many other functions.)
Platform: | Size: 18432 | Author: MMK1 | Hits:
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